专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5434815A Stress reduction for non-volatile memory cell 失效
标题翻译：非易失性记忆体的压力降低
公开(公告)号：US5434815A
公开(公告)日：1995-07-18
申请号：US184227
申请日：1994-01-19
申请人： George Smarandoiu , Steven J. Schumann , Tsung-Ching Wu
发明人： George Smarandoiu , Steven J. Schumann , Tsung-Ching Wu
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , G11C16/06 , G11C16/08 , G11C7/00
CPC分类号： G11C16/08
摘要： Non-volatile semiconductor core memory performance is enhanced by reduced stress on core memory cells. Stress is reduced by selectable application of bias voltages to the sense line under control of the word line. The word line is connected to an inverting device in turn connected to a transistor effective for grounding the gate of a variable threshold programmable transistor in the memory cell. Power down of the word line is reflected in synchronous power-down of the sense line. Additionally, with power down, the sense amplifier for the particular core memory cell is disconnected from a master latch circuit, which in turn is connected to a slave latch circuit for applying the previous sense amplifier output to an input/output buffer, in order to secure the data sensed in core memory during read operation. The invention further permits reduced word line voltages during erase operation on the sense line and the variable threshold programmable transistor.
摘要翻译：非易失性半导体核心存储器性能通过减少核心存储器单元的应力来增强。在字线控制下，通过选择性地向感测线施加偏置电压来减小应力。字线连接到反相器件，反相器件又连接到有效地将存储器单元中的可变阈值可编程晶体管的栅极接地的晶体管。字线的掉电反映在感测线的同步掉电中。此外，在断电时，用于特定核心存储器单元的读出放大器与主锁存电路断开，主锁存电路又连接到从锁存电路，用于将先前的读出放大器输出施加到输入/输出缓冲器，以便在读取操作期间保护在核心存储器中感测的数据。本发明还允许在感测线和可变阈值可编程晶体管的擦除操作期间减少字线电压。

12. 发明授权

US4851361A Fabrication process for EEPROMS with high voltage transistors 失效
标题翻译：具有高压晶体管的EEPROMS的制造工艺
公开(公告)号：US4851361A
公开(公告)日：1989-07-25
申请号：US152313
申请日：1988-02-04
申请人： Steven J. Schumann , John Y. Huang
发明人： Steven J. Schumann , John Y. Huang
IPC分类号： H01L21/8238 , H01L21/8247
CPC分类号： H01L27/11526 , H01L21/8238 , H01L27/11546
摘要： A CMOS fabrication process for EEPROMs having high-breakdown-voltage peripheral transistors in which a single implant step early in the process forms buried implants for both the memory cell's tunnel area source and the high voltage transistor's source and drain areas. The single implant step can be formed either before or after the formation of the channel stops and field oxide around the devices. The floating gate of the memory cell and the gates of the other devices are formed with polysilicon, the gates of the high voltage transistor overlapping the buried implants of its source and drain. The sources and drains of the other peripheral devices are then formed, using their polysilicon gates as a self-aligning mask. This may also include the formation of contact source and drain for the high voltage transistor. The process concludes with the formation of one or two layers of conductive lines connecting to specified drains, sources and gates to form a desired circuit pattern.
摘要翻译：用于具有高击穿电压外围晶体管的EEPROM的CMOS制造工艺，其中该工艺早期的单个注入步骤为存储器单元的隧道区域源和高压晶体管的源极和漏极区域形成埋入的植入物。单个注入步骤可以在通道形成之前或之后形成，并且在器件周围形成场氧化物。存储单元的浮置栅极和其他器件的栅极由多晶硅形成，高压晶体管的栅极与其源极和漏极的埋入式植入物重叠。然后，使用其多晶硅栅极作为自对准掩模来形成其它外围器件的源极和漏极。这也可能包括形成高压晶体管的接触源极和漏极。该过程的结论是形成连接到指定的漏极，源极和栅极的一层或两层导线，以形成所需的电路图案。

13. 发明授权

US4764899A Writing speed in multi-port static rams 失效
标题翻译：在多端口静态公差中写入速度
公开(公告)号：US4764899A
公开(公告)日：1988-08-16
申请号：US827994
申请日：1986-02-07
申请人： Kent D. Lewallen , Steven J. Schumann
发明人： Kent D. Lewallen , Steven J. Schumann
IPC分类号： G11C8/16 , G11C7/00
CPC分类号： G11C8/16
摘要： A write-bias gate in the form of an FET is provided for each of the bit-lines. Each FET has its drain electrode connected to logic 1 and its source electrode connected to the bit-line. When one port is writing, the write-bias gates on the other port(s) are driven by a signal which causes them to enter a pass condition, supplying extra current to pull up the bit lines of the non-writing port(s).
摘要翻译：为每个位线提供了FET形式的写偏置栅极。每个FET的漏电极连接到逻辑1，其源电极连接到位线。当一个端口正在写入时，另一个端口上的写偏置门由一个使其进入通过条件的信号驱动，提供额外的电流来上拉非写入端口的位线，。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式