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11. 发明授权

US07910429B2 Method of forming ONO-type sidewall with reduced bird's beak 有权
标题翻译：用鸟喙形成ONO型侧壁的方法
公开(公告)号：US07910429B2
公开(公告)日：2011-03-22
申请号：US10821100
申请日：2004-04-07
申请人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao , George Kovall , Steven Ming Yang
发明人： Zhong Dong , Chuck Jang , Ching-Hwa Chen , Chunchieh Huang , Jin-Ho Kim , Vei-Han Chan , Chung Wai Leung , Chia-Shun Hsiao , George Kovall , Steven Ming Yang
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L29/42328 , H01L29/513 , H01L29/7881
摘要： Conventional fabrication of sidewall oxide around an ONO-type memory cell stack usually produces Bird's Beak because prior to the fabrication, there is an exposed sidewall of the ONO-type memory cell stack that exposes side parts of a plurality of material layers respectively composed of different materials. Certain materials in the stack such as silicon nitrides are more difficult to oxidize than other materials in the stack such polysilicon. As a result oxidation does not proceed uniformly along the multi-layered height of the sidewall. The present disclosure shows how radical-based fabrication of sidewall dielectric can help to reduce the Bird's Beak formation. More specifically, it is indicated that short-lived oxidizing agents (e.g., atomic oxygen) are able to better oxidize difficult to oxidize materials such as silicon nitride and the it is indicated that the short-lived oxidizing agents alternatively or additionally do not diffuse as deeply through already oxidized layers of the sidewall such as silicon oxide layers. As a result, a more uniform sidewall dielectric can be fabricated with more uniform breakdown voltages along it height.
摘要翻译：通常在ONO型存储单元堆叠周围制造侧壁氧化物通常产生鸟喙，因为在制造之前，存在ONO型存储单元堆叠的暴露的侧壁，其暴露分别由不同的多个材料层组成的多个材料层的侧面部分材料堆叠中的某些材料如氮化硅比堆叠中的其它材料更难以氧化，这样的多晶硅。结果，氧化不沿着侧壁的多层高度均匀地进行。本公开显示了基于侧壁电介质的基于基础的制造有助于减少鸟喙形成。更具体地，表明短寿命氧化剂（例如原子氧）能够更好地氧化难以氧化的材料如氮化硅，并且表明短寿命氧化剂交替地或另外不扩散为深深地通过侧壁的已氧化层，例如氧化硅层。结果，可以制造更均匀的侧壁电介质，沿其高度具有更均匀的击穿电压。

12. 发明授权

US07001810B2 Floating gate nitridation 有权
公开(公告)号：US07001810B2
公开(公告)日：2006-02-21
申请号：US10769025
申请日：2004-01-30
申请人： Zhong Dong , Chuck Jang , Ching-Hwa Chen
发明人： Zhong Dong , Chuck Jang , Ching-Hwa Chen
IPC分类号： H01L21/336 , H01L21/26
CPC分类号： H01L29/66825 , H01L21/28273
摘要： The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.

13. 发明申请

US20060008997A1 Atomic layer deposition of interpoly oxides in a non-volatile memory device 审中-公开
公开(公告)号：US20060008997A1
公开(公告)日：2006-01-12
申请号：US11197562
申请日：2005-08-04
申请人： Chuck Jang , Zhong Dong , Vei-Han Chan , Ching-Hwa Chen
发明人： Chuck Jang , Zhong Dong , Vei-Han Chan , Ching-Hwa Chen
IPC分类号： H01L21/336
CPC分类号： H01L21/02164 , H01L21/02178 , H01L21/022 , H01L21/02211 , H01L21/02271 , H01L21/0228 , H01L21/02307 , H01L21/28211 , H01L21/3162 , H01L21/31683 , H01L29/40114 , H01L29/511
摘要： Aluminum oxide is deposited by atomic layer deposition to form a high-k dielectric for the interpoly dielectric layer of a non-volatile memory device. The increased capacitive coupling can allow a thicker oxide layer to be used between the floating gate and the control gate, resulting in improved reliability and longer lifetime of the memory cells fabricated according to this invention.

14. 发明授权

US06881668B2 Control of air gap position in a dielectric layer 有权
标题翻译：控制电介质层中的气隙位置
公开(公告)号：US06881668B2
公开(公告)日：2005-04-19
申请号：US10655706
申请日：2003-09-05
申请人： Tai-Peng Lee , Ching-Yueh Hu , Chuck Jang
发明人： Tai-Peng Lee , Ching-Yueh Hu , Chuck Jang
IPC分类号： H01L21/768 , H01L23/522 , H01L21/76 , H01L21/44
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , Y10T428/3154 , H01L2924/00
摘要： A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at least two features and a substrate and an air gap is formed between the at least two features and above the feature height. The first dielectric layer is etched between the at least two features to open the air gap. Then a second dielectric layer is deposited over the etched first dielectric layer to form an air gap between the at least two features and completely below the feature height.
摘要翻译：一种用于控制导电线之间的金属间电介质层中的气隙的位置和使用这种方法形成的结构的方法。在至少两个特征和基底上沉积第一介电层，并且在所述至少两个特征之间并且高于特征高度形成气隙。第一介电层在至少两个特征之间被蚀刻以打开气隙。然后，在蚀刻的第一介电层上沉积第二电介质层，以在至少两个特征之间形成气隙并完全低于特征高度。

15. 发明申请

US20050051865A1 Control of air gap position in a dielectric layer 有权
公开(公告)号：US20050051865A1
公开(公告)日：2005-03-10
申请号：US10921041
申请日：2004-08-17
申请人： Tai-Peng Lee , Ching-Yueh Hu , Chuck Jang
发明人： Tai-Peng Lee , Ching-Yueh Hu , Chuck Jang
IPC分类号： H01L21/768 , H01L23/522 , H01L29/00
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , Y10T428/3154 , H01L2924/00
摘要： A method for controlling the position of air gaps in intermetal dielectric layers between conductive lines and a structure formed using such a method. A first dielectric layer is deposited over at least two features and a substrate and an air gap is formed between the at least two features and above the feature height. The first dielectric layer is etched between the at least two features to open the air gap. Then a second dielectric layer is deposited over the etched first dielectric layer to form an air gap between the at least two features and completely below the feature height.

16. 发明申请

US20050003630A1 Trench isolation without grooving 有权
标题翻译：沟槽隔离无槽
公开(公告)号：US20050003630A1
公开(公告)日：2005-01-06
申请号：US10901948
申请日：2004-07-29
申请人： Hua Ji , Dong Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.
摘要翻译：提供了一种形成没有沟槽氧化物开槽的浅沟槽隔离区的方法和结构。特别地，一种方法包括两步氧化法，其中氧化物衬垫在沟槽的内表面上划线，并且沟槽填充有本体氧化物层，优选使用高密度等离子体化学气相沉积（HDP-CVD）工艺。氧化物衬垫和本体氧化物层被形成为具有相似的蚀刻速率。因此，当在堆叠结构之间蚀刻氧化物衬垫和本体氧化物层时，形成基本平坦且没有凹槽的公共电介质顶表面。

17. 发明授权

US06787409B2 Method of forming trench isolation without grooving 有权
标题翻译：无沟槽形成沟槽隔离的方法
公开(公告)号：US06787409B2
公开(公告)日：2004-09-07
申请号：US10305464
申请日：2002-11-26
申请人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
发明人： Hua Ji , Dong Jun Kim , Jin-Ho Kim , Chuck Jang
IPC分类号： H01L218238
CPC分类号： H01L21/76229
摘要： A method and structure to form shallow trench isolation regions without trench oxide grooving is provided. In particular, a method includes a two-step oxide process in which an oxide liner lines the inside surface of a trench and the trench is filled with a bulk oxide layer, preferably using a high density plasma chemical vapor deposition (HDP-CVD) process. The oxide liner and the bulk oxide layer are formed to have similar etch rates. Thus, when etching the oxide liner and the bulk oxide layer between stack structures, a common dielectric top surface is formed that is substantially planar and without grooves.
摘要翻译：提供了一种形成没有沟槽氧化物开槽的浅沟槽隔离区的方法和结构。特别地，一种方法包括两步氧化法，其中氧化物衬垫在沟槽的内表面上划线，并且沟槽填充有本体氧化物层，优选使用高密度等离子体化学气相沉积（HDP-CVD）工艺。氧化物衬垫和本体氧化物层被形成为具有相似的蚀刻速率。因此，当在堆叠结构之间蚀刻氧化物衬垫和本体氧化物层时，形成基本平坦且没有凹槽的公共电介质顶表面。

18. 发明授权

US5618756A Selective WSix deposition 失效
标题翻译：选择性WSix沉积
公开(公告)号：US5618756A
公开(公告)日：1997-04-08
申请号：US639391
申请日：1996-04-29
申请人： Peter Chew , Chuck Jang
发明人： Peter Chew , Chuck Jang
IPC分类号： H01L21/285 , H01L21/768 , H01L21/312 , H01L21/44
CPC分类号： H01L21/76879 , H01L21/28518
摘要： A method for selectively depositing WSi.sub.x is described. Semiconductor device structures are provided in and on a semiconductor substrate wherein WSi.sub.x is to be deposited overlying a first portion of the substrate and wherein WSi.sub.x is not to be deposited overlying a second portion of the substrate. A layer of organic material is provided over the surface of the substrate overlying the second portion of the substrate. A layer of WSi.sub.x is deposited over the surface of the substrate wherein the WSi.sub.x is deposited overlying the first portion of the substrate and wherein the presence of the organic material layer prevents the WSi.sub.x from depositing overlying the second portion of the substrate completing the selective WSi.sub.x deposition in the fabrication of an integrated circuit device.
摘要翻译：描述了一种用于选择性地放置WSix的方法。半导体器件结构设置在半导体衬底中和之上，其中WSix将被沉积在衬底的第一部分上，并且其中WSix不被沉积覆盖在衬底的第二部分上。在衬底的覆盖衬底的第二部分的表面上方提供一层有机材料。一层WSix沉积在衬底的表面上，其中WSix沉积在衬底的第一部分上，并且其中有机材料层的存在防止WSix沉积覆盖衬底的第二部分，从而完成选择性WSix沉积在制造集成电路器件时。

19. 发明授权

US07323729B2 Methods for improving quality of high temperature oxide (HTO) formed from halogen-containing precursor and products thereof and apparatus therefor 有权
标题翻译：用于提高由含卤素前体及其产物形成的高温氧化物（HTO）的质量的方法及其设备
公开(公告)号：US07323729B2
公开(公告)日：2008-01-29
申请号：US11431087
申请日：2006-05-04
申请人： Zhong Dong , Chuck Jang , Chia-Shun Hsiao
发明人： Zhong Dong , Chuck Jang , Chia-Shun Hsiao
IPC分类号： H01L29/76
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02337 , H01L21/28158 , H01L21/3105 , H01L21/31612
摘要： A method and apparatus are disclosed for reducing the concentration of chlorine and/or other bound contaminants within a semiconductor oxide composition that is formed by chemical vapor deposition (CVD) using a semiconductor-element-providing reactant such as dichlorosilane (DCS) and an oxygen-providing reactant such as N2O. In one embodiment, a DCS-HTO film is annealed by heating N2O gas to a temperature in the range of about 825° C. to about 950° C. so as to trigger exothermic decomposition of the N2O gas and flowing the heated gas across the DCS-HTO film so that disassociated atomic oxygen radicals within the heated N2O gas can transfer disassociating energy to chlorine atoms bound within the DCS-HTO film and so that the atomic oxygen radicals can fill oxygen vacancies within the semiconductor-oxide matrix of DCS-HTO film. An improved ONO structure may be formed with the annealed DCS-HTO film for use in floating gate or other memory applications.
摘要翻译：公开了一种方法和装置，用于降低通过化学气相沉积（CVD）形成的半导体氧化物组合物中的氯和/或其它结合的污染物的浓度，所述半导体氧化物组合物使用提供半导体元素的反应物如二氯硅烷（DCS）和氧提供反应物如N 2 O。在一个实施方案中，通过将N 2 O 2气体加热至约825℃至约950℃的温度来退火DCS-HTO膜，以引发放热分解 N 2 O气体并使加热的气体流过DCS-HTO膜，使得加热的N 2 O气体内的解离的原子氧自由基能够将分解能量转移到结合的氯原子上在DCS-HTO膜内，使得原子氧自由基可以填充DCS-HTO膜的半导体氧化物基质内的氧空位。可以用退火的DCS-HTO膜形成改进的ONO结构，用于浮动栅极或其他存储器应用中。

20. 发明申请

US20070264776A1 Precision creation of inter-gates insulator 审中-公开
公开(公告)号：US20070264776A1
公开(公告)日：2007-11-15
申请号：US11801301
申请日：2007-05-08
申请人： Zhong Dong , Chuck Jang , Chunchieh Huang
发明人： Zhong Dong , Chuck Jang , Chunchieh Huang
IPC分类号： H01L21/336
CPC分类号： H01L29/511 , H01L29/40114
摘要： An ONO-type inter-poly insulator is formed by depositing intrinsic silicon on an oxidation stop layer. In one embodiment, the oxidation stop layer is a nitridated top surface of a lower, and conductively-doped, polysilicon layer. In one embodiment, atomic layer deposition (ALD) is used to precisely control the thickness of the deposited, intrinsic silicon. Heat and an oxidizing atmosphere are used to convert the deposited, intrinsic silicon into thermally-grown, silicon dioxide. The oxidation stop layer impedes deeper oxidation. A silicon nitride layer and an additional silicon oxide layer are further deposited to complete the ONO structure before an upper, and conductively-doped, polysilicon layer is formed. In one embodiment, the lower and upper polysilicon layers are patterned to respectively define a floating gate (FG) and a control gate (CG) of an electrically re-programmable memory cell. In an alternative embodiment, after the middle, silicon nitride of the ONO structure is defined, another layer of intrinsic silicon is deposited, by way of for example, ALD. Heat and an oxidizing atmosphere are used to convert the second deposited, intrinsic silicon into thermally-grown, silicon dioxide. An ONO structure with two thermally-grown, and spaced apart, silicon oxide layers is thereby provided.

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