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11. 发明申请

US20070141082A1 Cell surface expression vector of parvovirus antigen and microorganisms transformed thereof 审中-公开
标题翻译：细小病毒抗原的细胞表面表达载体及其转化的微生物
公开(公告)号：US20070141082A1
公开(公告)日：2007-06-21
申请号：US10588359
申请日：2005-02-04
申请人： Moon-Hee Sung , Chul Kim , Chang Jung , Seung Hong , Jong Lee , Jae Choi , Motomitsu Sewaki , Jong Kim
发明人： Moon-Hee Sung , Chul Kim , Chang Jung , Seung Hong , Jong Lee , Jae Choi , Motomitsu Sewaki , Jong Kim
IPC分类号： A61K39/155 , C12N15/74 , C12N1/21
CPC分类号： C07K14/005 , C12N15/74 , C12N2750/14322
摘要： The present invention relates to a surface expression vector expressing a parvovirus antigen on the surface of microorganisms, the vector containing not only a gene encoding the capsid antigen protein of parvovirus causing canine parvovirus (CPV) infection and feline panleukopenia (FLP) but also at least one of pgsB, pgsC and pgsA genes encoding a poly-gamma-glutamate synthetase complex. Also, the present invention relates to microorganisms transformed with the surface expression vector, and parvovirus vaccines containing the transformed microorganisms. According to the present invention, the use of the recombinant bacterial strains expressing the parvovirus antigen on their surface allows the economical production of vaccines for the treatment and prevention of canine parvovirus infection and feline panleukopenia.
摘要翻译：本发明涉及表达微生物表面细小病毒抗原的表面表达载体，该载体不仅包含编码引起犬细小病毒（CPV）感染和猫泛白细胞减少症（FLP）的细小病毒的衣壳抗原蛋白的基因，而且至少编码聚-γ-谷氨酸合成酶复合物的pgsB，pgsC和pgsA基因之一。此外，本发明涉及用表面表达载体转化的微生物，以及含有转化的微生物的细小病毒疫苗。根据本发明，在其表面上使用表达细小病毒抗原的重组细菌菌株可以经济地生产用于治疗和预防犬细小病毒感染和猫泛白细胞减少症的疫苗。

12. 发明申请

US20070130568A1 Adaptive execution method for multithreaded processor-based parallel system 有权
标题翻译：基于多线程处理器的并行系统的自适应执行方法
公开(公告)号：US20070130568A1
公开(公告)日：2007-06-07
申请号：US11453288
申请日：2006-06-15
申请人： Chang Jung , Dae Lim , Jae Lee , Sang Han
发明人： Chang Jung , Dae Lim , Jae Lee , Sang Han
IPC分类号： G06F9/46
CPC分类号： G06F8/456 , G06F9/5066 , G06F11/3404 , G06F2201/88
摘要： Provided is a parallel program execution method in which in order to reflect structural characteristics of a multithreaded processor-based parallel system, performance of the parallel loop is predicted while compiling or executing using a performance prediction model and then the parallel program is executed using an adaptive execution method. The method includes the steps of: generating as many threads as the number of physical processors of the parallel system in order to execute at least one parallel loop contained in the parallel program; by the generated threads, executing at least one single loop of each parallel loop; measuring an execution time, the number of executed instructions, and the number of cache misses for each parallel loop; determining an execution mode of each parallel loop by determining the number of threads used to execute each parallel loop based on the measured values; and allocating the threads to each physical processor according to the result of the determination to execute each parallel loop. The method significantly improves the performance of the parallel program driven in the multithreaded processor-based parallel system.
摘要翻译：提供了一种并行程序执行方法，其中为了反映基于多线程处理器的并行系统的结构特征，在使用性能预测模型编译或执行时预测并行循环的性能，然后使用自适应执行方式。该方法包括以下步骤：生成与并行系统的物理处理器的数量一样多的线程，以便执行并行程序中包含的至少一个并行循环; 通过生成的线程执行每个并行循环的至少一个单个循环; 测量执行时间，执行指令的数量以及每个并行循环的高速缓存未命中数; 通过基于测量值确定用于执行每个并行循环的线程数，确定每个并行循环的执行模式; 以及根据确定的结果将线程分配给每个物理处理器以执行每个并行循环。该方法显着提高了在基于多线程处理器的并行系统中驱动的并行程序的性能。

13. 发明申请

US20060274585A1 Memory device with row shifting for defective row repair 审中-公开
标题翻译：具有行移位的存储器件，用于有缺陷的行修复
公开(公告)号：US20060274585A1
公开(公告)日：2006-12-07
申请号：US11145425
申请日：2005-06-03
申请人： Chang Jung
发明人： Chang Jung
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： A memory device includes N regular rows of memory cells, L redundant rows of memory cells, a shift circuit, and N word lines, where N>1 and L>1. Each word line is associated with a designated row and an alternate row that is L rows away from the designated row. The shift circuit receives the N word lines and couples each word line to either the designated row or the alternate row for that word line. If L is two, then the shift circuit couples even-numbered word lines to even-numbered rows and odd-numbered word lines to odd-numbered rows. The shift circuit may couple each word line to (1) the designated row if this row is non-defective and a preceding word line is not shifted down or (2) the alternate row otherwise.
摘要翻译：存储器件包括N个常规行的存储器单元，L个冗余的存储单元行，移位电路和N个字线，其中N> 1和L> 1。每个字线与指定行和与指定行相距L列的替代行相关联。移位电路接收N个字线，并将每个字线耦合到该字线的指定行或替代行。如果L为2，则移位电路将偶数字线偶数行和奇数字线耦合到奇数行。如果该行是无缺陷的并且先前的字线没有向下移动，或者（2）替代行，移位电路可以将每个字线耦合到（1）指定的行。

14. 发明申请

US20050099864A1 Metal programmable self-timed memories 失效
标题翻译：金属可编程自定时存储器
公开(公告)号：US20050099864A1
公开(公告)日：2005-05-12
申请号：US10706110
申请日：2003-11-12
申请人： Jeffrey Brown , Chang Jung
发明人： Jeffrey Brown , Chang Jung
IPC分类号： G11C5/02 , G11C8/10 , G11C11/417 , G11C7/00
CPC分类号： G11C8/10 , G11C5/025 , G11C11/417
摘要： A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.
摘要翻译：公开了一种自定时存储器阵列，其中支持可分割性和金属可编程性，同时最小化布局空间。自定时行解码器电路放置在与相应I / O块相邻的阵列的顶部和底部。自定时信号从阵列的顶部（相应的底部）路由到存储器阵列的中途（分别向上）一点，然后返回到顶部（相应的底部）的自定时行解码器阵列。也可以使用相同的方法来解释从阵列的底部（相对顶部）到I / O块中的读出放大器的位线延迟。通过从不需要的存储器单元中消除金属布线层来提供电线布线的进一步的灵活性，并且可以使用可编程门阵列来允许为存储器选择任意的字大小。

15. 发明授权

US07400543B2 Metal programmable self-timed memories 失效
标题翻译：金属可编程自定时存储器
公开(公告)号：US07400543B2
公开(公告)日：2008-07-15
申请号：US10706110
申请日：2003-11-12
申请人： Jeffrey Scott Brown , Chang Jung
发明人： Jeffrey Scott Brown , Chang Jung
IPC分类号： G11C7/02
CPC分类号： G11C8/10 , G11C5/025 , G11C11/417
摘要： A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing signal is routed from the top (resp. bottom) of the array to a point halfway down (resp. up) the memory array and then back to a self-timing row decoder at the top (resp. bottom) of the array. The same approach may also be used to account for the bitline wire delay from the bottom (resp. top) of the array to the sense amplifiers in the I/O block. Further flexibility in wire routing is provided by eliminating metal routing layers from unneeded memory cells, and a programmable gate array may be used to allow an arbitrary word size to be chosen for the memory.
摘要翻译：公开了一种自定时存储器阵列，其中支持可分割性和金属可编程性，同时最小化布局空间。自定时行解码器电路放置在与相应I / O块相邻的阵列的顶部和底部。自定时信号从阵列的顶部（相应的底部）路由到存储器阵列的中途（分别向上）一点，然后返回到顶部（相应的底部）的自定时行解码器阵列。也可以使用相同的方法来解释从阵列的底部（相对顶部）到I / O块中的读出放大器的位线延迟。通过从不需要的存储器单元中消除金属布线层来提供电线布线的进一步的灵活性，并且可以使用可编程门阵列来允许为存储器选择任意的字大小。

16. 发明申请

US20070275663A1 Cdma signal generator using an awgn generator and a saw filter 审中-公开
标题翻译： Cdma信号发生器采用awgn发生器和锯式滤波器
公开(公告)号：US20070275663A1
公开(公告)日：2007-11-29
申请号：US10560769
申请日：2004-07-26
申请人： Chang Jung
发明人： Chang Jung
IPC分类号： H04B17/00
CPC分类号： H04B17/16
摘要： There is provided a CDMA generator using an AWGN generator and a SAW filter. The CDMA generator according to the present invention comprises (1) an additive white Gaussian noise generator for generating a first broad band noise in an RF receiving band, (2) a first signal generator for generating a first conversion frequency signal, (3) a first mixer for mixing the first broad band noise in the RF receiving band with the first conversion frequency signal to provide a second broad band noise in an IF band, the IF band including a CDMA band and a remaining frequency band that is exclusive of the CDMA band, (4) a SAW filter for attenuating a third broad band noise in the remaining frequency band within the IF band to a predetermined level to provide a substantially CDMA band noise, (5) a second signal generator for generating a second conversion frequency signal, and (6) a second mixer for mixing the substantially CDMA band noise from the SAW filter with the second conversion frequency signal from the second signal generator to provide an output, wherein the output is usable as a test input signal to an RF block unit.
摘要翻译：提供了使用AWGN发生器和SAW滤波器的CDMA发生器。根据本发明的CDMA发生器包括（1）用于在RF接收频带中产生第一宽带噪声的加性白高斯噪声发生器，（2）用于产生第一转换频率信号的第一信号发生器，（3）第一混频器，用于将RF接收频带中的第一宽带噪声与第一转换频率信号混合，以在IF频带中提供第二宽频带噪声，所述IF频带包括CDMA频带和除CDMA之外的剩余频带（4）用于将IF频带内的剩余频带中的第三宽频带噪声衰减到预定电平以提供基本CDMA频带噪声的SAW滤波器，（5）用于产生第二转换频率信号的第二信号发生器，和（6）第二混频器，用于将来自SAW滤波器的基本CDMA频带噪声与来自第二信号发生器的第二转换频率信号混合以提供输出，其中输出可用作到RF块单元的测试输入信号。

17. 发明申请

US20070109909A1 Pseudo-dual port memory where ratio of first to second memory access is clock duty cycle independent 有权
标题翻译：伪双端口存储器，其中第一到第二存储器访问的比率是时钟占空比独立的
公开(公告)号：US20070109909A1
公开(公告)日：2007-05-17
申请号：US11282333
申请日：2005-11-17
申请人： Chang Jung
发明人： Chang Jung
IPC分类号： G11C8/18
CPC分类号： G11C8/18 , G11C7/1012 , G11C7/1039 , G11C7/1042 , G11C7/22 , G11C7/222 , G11C8/16
摘要： A pseudo-dual port memory performs both a first memory access operation and a second memory access operation in a single period of an externally supplied clock signal CLK. The signal CLK is used to latch a first address for the first operation and a second address for the second operation. Control circuitry generates first control signals that initiate the first operation. The time duration of the first operation depends upon a delay through a delay circuit. A precharge period follows termination of the first operation. The time duration of the precharge period depends upon a propagation delay through the control circuit. The memory access of the second operation is initiated following termination of the precharging. The time duration of the second memory access depends on a delay through the delay circuit. The time when the second operation is initiated is independent of the duty cycle of CLK.
摘要翻译：伪双端口存储器在外部提供的时钟信号CLK的单个周期中执行第一存储器存取操作和第二存储器存取操作。信号CLK用于锁存用于第一操作的第一地址和用于第二操作的第二地址。控制电路产生启动第一操作的第一控制信号。第一操作的持续时间取决于通过延迟电路的延迟。在第一次操作结束之后的预充电期间。预充电周期的持续时间取决于通过控制电路的传播延迟。第二次操作的存储器访问在预充电结束后启动。第二存储器访问的持续时间取决于延迟电路的延迟。启动第二个操作的时间与CLK的占空比无关。

18. 发明申请

US20070054050A1 Photoresist coating apparatus and method 审中-公开
标题翻译：光刻胶涂布装置及方法
公开(公告)号：US20070054050A1
公开(公告)日：2007-03-08
申请号：US11372376
申请日：2006-03-10
申请人： Jin Lee , Jun Koo , Seong Kim , Tae Kim , Tae Park , Chang Jung , Dong Lee
发明人： Jin Lee , Jun Koo , Seong Kim , Tae Kim , Tae Park , Chang Jung , Dong Lee
IPC分类号： B05B5/025 , B05C11/02 , C23C16/00
CPC分类号： C23C26/00 , H01L21/6715
摘要： A photoresist coating apparatus and method for solving an edge bead problem occurring in photoresist coating. An edge bead is prevented from occurring by forming a solvent vapor layer from ionized solvent vapor on a wafer through the use of a magnetic field generator, spraying a liquid photoresist on the wafer, and controlling the liquid photoresist to not vaporize more at the edge of the wafer than towards the center thereof. A photoresist coating apparatus includes: a solvent ionizer supplying ionized solvent vapor; and a magnetic field generator forming a solvent vapor layer on a wafer from the ionized solvent vapor.
摘要翻译：一种用于解决在光致抗蚀剂涂层中出现的边缘珠问题的光致抗蚀剂涂覆装置和方法。通过使用磁场发生器，在晶片上喷射液态光致抗蚀剂，并且在液晶光致抗蚀剂的边缘处喷射液态光致抗蚀剂，从而在晶片上形成溶剂蒸汽层晶片比其中心。光致抗蚀剂涂布装置包括：提供离子化溶剂蒸气的溶剂离子发生器; 以及磁场发生器，从电离溶剂蒸气在晶片上形成溶剂蒸汽层。

19. 发明申请

US20050007837A1 Clock generator for pseudo dual port memory 有权
标题翻译：时钟发生器用于伪双端口存储器
公开(公告)号：US20050007837A1
公开(公告)日：2005-01-13
申请号：US10911457
申请日：2004-08-04
申请人： Chang Jung
发明人： Chang Jung
IPC分类号： G11C7/22 , G11C7/00
CPC分类号： G11C7/222 , G11C7/22
摘要： A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.
摘要翻译：用于伪双端口存储器的时钟产生电路包含反馈，延迟和锁存器，以确保写（读）操作时钟脉冲在时间上与读（写）操作时钟充分间隔开。时钟产生电路接收外部时钟，读使能信号，写使能信号和复位信号作为输入。优点包括最小化时钟周期时间和不受外部时钟占空比的影响。可以添加延迟电路，使得所生成的时钟信号具有足够的扇出并且足够稳定。

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