专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US5506982A Data processing system generating clock signal from an input clock, phase locked to the input clock and used for clocking logic devices 失效
公开(公告)号：US5506982A
公开(公告)日：1996-04-09
申请号：US278245
申请日：1994-07-21
申请人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
发明人： Takashi Hotta , Kozaburo Kurita , Masahiro Iwamura , Hideo Maejima , Shigeya Tanaka , Tadaaki Bandoh , Yasuhiro Nakatsuka , Kazuo Kato , Sin-ichi Sinoda
IPC分类号： G06F1/10 , H03K5/156 , H03L7/18 , G06F1/06
CPC分类号： H03K5/1565 , G06F1/10 , H03L7/18
摘要： An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.

12. 发明授权

US5398318A High speed, low noise output buffer with non-identical pairs of output transistors 失效
标题翻译：具有不相同输出晶体管对的高速，低噪声输出缓冲器
公开(公告)号：US5398318A
公开(公告)日：1995-03-14
申请号：US608370
申请日：1990-11-02
申请人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
发明人： Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
IPC分类号： G11C11/417 , G11C11/409 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/08 , H03K19/088 , H03K19/0944 , G06F13/00
CPC分类号： H03K19/09448 , H03K17/164 , H03K19/00361
摘要： An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
摘要翻译：提供了一种改进的缓冲电路装置，其特别适用于半导体集成电路半导体存储器和微处理器。缓冲电路能够切换各种类型的LSI中的大负载，并且具有低噪声和高速电路操作。这通过输出缓冲器电路中的输出晶体管的并联连接，并且通过区分并联连接的输出晶体管之间的操作的起始时间而不使用延迟电路来实现。例如，通过提供具有彼此不同特性的晶体管或具有彼此不同特性的驱动电路，可以实现区分起始时间。电路的另一方面是提供两级预置布置，其在施加输入信号之前将电路的输出节点预设为预定值。

13. 发明授权

US5378941A Bipolar transistor MOS transistor hybrid semiconductor integrated circuit device 失效
标题翻译：双极晶体管MOS晶体管混合半导体集成电路器件
公开(公告)号：US5378941A
公开(公告)日：1995-01-03
申请号：US983467
申请日：1992-11-30
申请人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
发明人： Yoji Nishio , Ikuro Masuda , Kazuo Kato , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L21/331 , H01L21/82 , H01L21/8249 , H01L27/06 , H01L27/118 , H01L29/73 , H03K19/173 , H03K19/02 , H03K19/084
CPC分类号： H01L27/11896
摘要： A high speed and low power consumption semiconductor integrated circuit device has a plurality of internal circuits each including circuit elements for performing a desired circuit operation, a plurality of input circuits for receiving external input signals and supplying the signals to the internal circuits and a plurality of output circuits for receiving the output signals from the internal circuits and supplying signals to an external circuit. Each of the internal circuits is primarily constructed by bipolar transistors and MOS transistors, and at least one of each of the input circuits and each of the output circuits is primarily constructed by bipolar transistors.
摘要翻译：高速低功耗半导体集成电路器件具有多个内部电路，每个内部电路包括用于执行期望的电路操作的电路元件，用于接收外部输入信号并将信号提供给内部电路的多个输入电路和多个输出电路，用于接收来自内部电路的输出信号并向外部电路提供信号。每个内部电路主要由双极晶体管和MOS晶体管构成，并且每个输入电路和每个输出电路中的至少一个主要由双极晶体管构成。

14. 发明授权

US5153452A Bipolar-MOS IC with internal voltage generator and LSI device with internal voltage generator 失效
标题翻译：具有内部电压发生器和具有内部电压发生器的LSI器件的双极MOS IC
公开(公告)号：US5153452A
公开(公告)日：1992-10-06
申请号：US401849
申请日：1989-08-30
申请人： Masahiro Iwamura , Shigeya Tanaka , Tatsumi Yamauchi , Ikuro Masuda , Tetsuo Nakano
发明人： Masahiro Iwamura , Shigeya Tanaka , Tatsumi Yamauchi , Ikuro Masuda , Tetsuo Nakano
IPC分类号： H01L27/04 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/56 , H01L21/822 , H01L27/06
CPC分类号： G11C11/565 , G05F1/465 , G11C5/147 , G11C16/30
摘要： There are provided a bipolar-MOS IC device smaller than half-micron scale, and a combination of such IC device and external circuits. The IC device has an internal voltage generating circuit for generating an internal power source by using an external power source, the voltage of the internal power source being lower than that of the external power source. The internal voltage generating circuit includes an NPN transistor formed in an N-type region or N-type island within a P-type semiconductor substrate of the IC device, and a PMOS transistor formed in the N-type island. The collector of the NPN transistor and the source of the PMOS transistor are used as external power source terminals. The drain of the PMOS transistor is connected to the base of the NPN transistor. The gate is used as a control signal terminal. The emitter of the NPN transistor is used as an internal power source output terminal. A current path from the external power source input terminal and the internal power source output terminal is accordingly formed within the N-type island isolated from the P-type substrate.
摘要翻译：提供了小于半微米级的双极MOS集成电路，以及这些IC器件和外部电路的组合。 IC器件具有内部电压产生电路，用于通过使用外部电源产生内部电源，内部电源的电压低于外部电源的电压。内部电压产生电路包括形成在IC器件的P型半导体衬底内的N型区域或N型岛中的NPN晶体管和形成在N型岛中的PMOS晶体管。 NPN晶体管的集电极和PMOS晶体管的源极用作外部电源端子。 PMOS晶体管的漏极连接到NPN晶体管的基极。门用作控制信号端子。 NPN晶体管的发射极用作内部电源输出端子。因此，在与P型基板隔离的N型岛中形成从外部电源输入端子和内部电源输出端子的电流路径。

15. 发明授权

US5119314A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5119314A
公开(公告)日：1992-06-02
申请号：US442301
申请日：1989-11-28
申请人： Takashi Hotta , Masahiro Iwamura
发明人： Takashi Hotta , Masahiro Iwamura
IPC分类号： H01L21/822 , G06F17/50 , H01L21/82 , H01L21/8249 , H01L27/04 , H01L27/06 , H01L27/118
CPC分类号： H01L27/11896 , G06F17/5068 , Y10S257/923
摘要： A semiconductor integrated circuit device which can operate at high speed and involves a low power consumption and a high integration density, wherein a Bi-CMOS basic cell and a Bi-CMOS macro cell are employed to define a critical path and a CMOS basic cell and a CMOS macro cell are employed for a portion of the device other than the critical path.
摘要翻译：一种半导体集成电路器件，其可以高速工作并且具有低功耗和高集成密度，其中采用Bi-CMOS基本单元和Bi-CMOS宏单元来定义关键路径和CMOS基本单元，对于除关键路径之外的器件的一部分，采用CMOS宏单元。

16. 发明授权

US4890017A CMOS-BiCMOS gate circuit 失效
标题翻译： CMOS-BiCMOS门电路
公开(公告)号：US4890017A
公开(公告)日：1989-12-26
申请号：US127184
申请日：1987-12-01
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

17. 发明授权

US4719373A Gate circuit of combined field-effect and bipolar transistors 失效
标题翻译：组合场效应和双极晶体管的门电路
公开(公告)号：US4719373A
公开(公告)日：1988-01-12
申请号：US45216
申请日：1987-04-30
申请人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
发明人： Ikuro Masuda , Kazuo Kato , Takao Sasayama , Yoji Nishio , Shigeo Kuboki , Masahiro Iwamura
IPC分类号： H03K19/08 , H01L27/06 , H03K19/01 , H03K19/017 , H03K19/094 , H03K19/0944 , H03K19/0952 , H03K17/60 , H03K3/33
CPC分类号： H01L27/0623 , H03K19/01 , H03K19/01721 , H03K19/09448
摘要： A high-speed operation, low-power consumption gate circuit structure comprises a combination of complementary field-effect-transistors and bipolar transistors and discharge means for discharging accumulated charges from these transistors when the field-effect-transistors and bipolar transistors are turned off.

18. 发明申请

US20140191576A1 ELECTRIC STORAGE SYSTEM 审中-公开
标题翻译：电力储存系统
公开(公告)号：US20140191576A1
公开(公告)日：2014-07-10
申请号：US14122616
申请日：2012-05-25
申请人： Mitsutoshi Honda , Masahiro Iwamura , Motoo Futami , Hiroyuki Shoji , Takeshi Inoue
发明人： Mitsutoshi Honda , Masahiro Iwamura , Motoo Futami , Hiroyuki Shoji , Takeshi Inoue
IPC分类号： H02J1/10
CPC分类号： H02J1/102 , H01M10/482 , H02J7/1423 , H02J7/345 , H02M3/158 , Y02T10/7005 , Y02T10/7022 , Y10T307/516
摘要： An electric storage system includes at least two types of electric storage cells. A first electric storage unit is configured from a first electric storage cell, and a second electric storage unit is configured from a second electric storage cell. The first and second electric storage units are electrically connected to each other through a current controlling circuit.
摘要翻译：电存储系统包括至少两种类型的蓄电单元。第一蓄电单元由第一蓄电单元构成，第二蓄电单元由第二蓄电单元构成。第一和第二蓄电单元通过电流控制电路彼此电连接。

19. 发明授权

US07973405B2 Integrated circuit for driving semiconductor device and power converter 有权
标题翻译：用于驱动半导体器件和功率转换器的集成电路
公开(公告)号：US07973405B2
公开(公告)日：2011-07-05
申请号：US12784331
申请日：2010-05-20
申请人： Yoshimasa Takahashi , Naoki Sakurai , Masashi Yura , Masahiro Iwamura , Mutsuhiro Mori
发明人： Yoshimasa Takahashi , Naoki Sakurai , Masashi Yura , Masahiro Iwamura , Mutsuhiro Mori
IPC分类号： H01L23/34
CPC分类号： H01L25/072 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/162 , H01L2224/16225 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/73204 , H01L2224/73265 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01037 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01051 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/014 , H01L2924/09701 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19105 , H01L2924/19107 , H01L2924/30105 , H01L2924/30107 , H02M1/08 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： An integrated circuit for driving a semiconductor device, which is adaptable for demands, such as a higher output (larger current), a higher voltage, and a smaller loss, and has a small size, is produced at a low cost, and has high reliability. A power converter including such an integrated circuit is also provided. Circuit elements constituting a drive section of an upper arm drive circuit 212, a level shift circuit 20 including a current sensing circuit 210, a drive section of a lower arm drive circuit 222, and a drive signal processing circuit 224 are integrated and built in one high withstand voltage IC chip 200. Circuit elements constituting a final output stage buffer section 213 of the upper arm drive circuit 212 are built in a vertical p-channel MOS-FET chip 213p and a vertical n-channel MOS-FET chip 213n. Circuit elements constituting a final output stage buffer section 223 of the lower arm drive circuit 222 are built in a vertical p-channel MOS-FET chip 223p and a vertical n-channel MOS-FET chip 223n. Thus, a driver IC 2 is fabricated.
摘要翻译：以低成本生产用于驱动半导体器件的集成电路，其具有较高的输出（较大的电流），更高的电压和更小的损耗，并且尺寸更小的需求，并且具有高的可靠性。还提供了一种包括这种集成电路的功率转换器。构成上臂驱动电路212的驱动部的电路元件，包括电流检测电路210的电平移动电路20，下臂驱动电路222的驱动部以及驱动信号处理电路224被一体化并内置于一个构成上臂驱动电路212的最终输出级缓冲器部分213的电路元件内置在垂直p沟道MOS-FET芯片213p和垂直n沟道MOS-FET芯片213n中。构成下臂驱动电路222的最终输出级缓冲部分223的电路元件内置在垂直p沟道MOS-FET芯片223p和垂直n沟道MOS-FET芯片223n中。因此，制造驱动器IC2。

20. 发明授权

US07541758B2 MOS rectifying device, driving method thereof, and motor generator and motor vehicle using thereof 失效
标题翻译： MOS整流装置，其驱动方法以及使用其的电动发电机和汽车
公开(公告)号：US07541758B2
公开(公告)日：2009-06-02
申请号：US11206225
申请日：2005-08-18
申请人： Masamitsu Inaba , Shinji Shirakawa , Masahiro Iwamura
发明人： Masamitsu Inaba , Shinji Shirakawa , Masahiro Iwamura
IPC分类号： H02P25/30
CPC分类号： H02M7/219 , H02P9/30 , H02P2101/45
摘要： V-phase upper-arm open phase detecting circuit outputs a permission signal to allow U-phase lower-arm MOSFET to be conductive when the V-phase voltage is higher than the positive electrode potential. In response to this permission signal, U-phase lower-arm driver circuit drives U-phase lower-arm MOSFET. V-phase lower-arm open phase detecting circuit outputs a permission signal to allow U-phase upper-arm MOSFET to be conductive when the V-phase voltage is lower than the negative electrode potential. In response to this permission signal, U-phase upper-arm driver circuit drives U-phase upper-arm MOSFET.Thereby, a MOS rectifying device capable of rectifying even when an open phase occurs, a driving method thereof, and a motor vehicle using thereof can be provided.
摘要翻译：当V相电压高于正极电位时，V相上臂开路相位检测电路输出允许U相下臂MOSFET导通的允许信号。响应该许可信号，U相下臂驱动电路驱动U相下臂MOSFET。当V相电压低于负极电位时，V相下臂开路相位检测电路输出允许U相上臂MOSFET导通的允许信号。响应该允许信号，U相上臂驱动电路驱动U相上臂MOSFET。因此，可以提供即使在开放相位发生时能够进行整流的MOS整流装置，其驱动方法和使用其的机动车辆。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式