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11. 发明授权

US5990914A Generating an error signal when accessing an invalid memory page 失效
标题翻译：访问无效内存页面时产生错误信号
公开(公告)号：US5990914A
公开(公告)日：1999-11-23
申请号：US926425
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F11/07 , G06F13/16
CPC分类号： G06F11/0772 , G06F11/073 , G06F11/0745 , G06F3/14
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a page of graphics data in memory, and feature flags that may be used to customize the associated page. One of the feature flags is used as a Present Bit for a corresponding memory page. When the feature flag Present Bit is set, the memory page has been reserved in the physical memory for graphics data and an address translation may be carried out. When the feature flag Present Bit is clear, the memory page has not been reserved for graphics data in the physical memory and a determination must then be made whether to perform the translation or generate an error signal to the computer processor.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器中的图形数据页面的基地址的地址指针，以及可用于定制关联页面的特征标记。其中一个功能标志用作相应存储器页面的当前位。当特征标志当前位被设置时，存储器页面已被保留在用于图形数据的物理存储器中，并且可以执行地址转换。当特征标志当前位清除时，存储器页面尚未被保留用于物理存储器中的图形数据，然后必须确定是否执行转换或者向计算机处理器生成错误信号。

12. 发明授权

US5936640A Accelerated graphics port memory mapped status and control registers 失效
标题翻译：加速图形端口存储器映射状态和控制寄存器
公开(公告)号：US5936640A
公开(公告)日：1999-08-10
申请号：US941862
申请日：1997-09-30
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F12/10 , G06F15/00 , G06F12/06
CPC分类号： G06F3/14 , G06F12/1027 , G06F12/1081
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. A plurality of AGP memory-mapped status and control registers are stored in the computer system memory, and are used for status and control of AGP functions in the computer system.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。多个AGP存储器映射状态和控制寄存器存储在计算机系统存储器中，用于计算机系统中AGP功能的状态和控制。

13. 发明授权

US5914727A Valid flag for disabling allocation of accelerated graphics port memory space 失效
标题翻译：禁止分配加速图形端口内存空间的有效标志
公开(公告)号：US5914727A
公开(公告)日：1999-06-22
申请号：US925773
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F12/02 , G06F12/10 , H04N7/26 , H04N7/50 , G06F15/16
CPC分类号： G06F12/1081 , G06F12/0292 , H04N19/423 , H04N19/61
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST. An AGP Valid bit is set to indicate whether an AGP device is present or not. If the AGP device is not present, then no virtual memory address space is allocated during the computer system startup.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址启动或POST。 AGP有效位设置为指示AGP设备是否存在。如果AGP设备不存在，则在计算机系统启动期间不会分配虚拟内存地址空间。

14. 发明授权

US5550989A Bridge circuit that can eliminate invalid data during information transfer between buses of different bitwidths 失效
标题翻译：桥接电路可以在不同位宽的总线之间的信息传输过程中消除无效数据
公开(公告)号：US5550989A
公开(公告)日：1996-08-27
申请号：US69234
申请日：1993-05-28
申请人： Gregory N. Santos
发明人： Gregory N. Santos
IPC分类号： G06F13/36 , G06F13/28 , G06F13/40 , G06F13/00
CPC分类号： G06F13/4018 , G06F13/28
摘要： Hardware logic within a host bridge that connects a CPU local bus to a peripheral bus that determines if data to be transmitted on the CPU local bus is non-contiguous and, if so, substitutes contiguous data for the non-contiguous data to ensure that the CPU local bus does not malfunction. Simultaneously, the hardware translates data transfers between a peripheral bus that is limited by its architecture to data strings of a standard length and a CPU local bus that permits dynamic bus sizing.
摘要翻译：将CPU本地总线连接到外围总线的主桥内的硬件逻辑，用于确定要在CPU本地总线上传输的数据是否不连续，如果是，则将连续的数据替换为不连续的数据，以确保 CPU本地总线不会发生故障。同时，硬件将受其架构限制的外围总线与标准长度的数据串和允许动态总线大小调整的CPU本地总线之间的数据传输进行转换。

15. 发明授权

US6078338A Accelerated graphics port programmable memory access arbiter 失效
标题翻译：加速图形端口可编程存储器访问仲裁器
公开(公告)号：US6078338A
公开(公告)日：2000-06-20
申请号：US38412
申请日：1998-03-11
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Gary J. Piccirillo
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Gary J. Piccirillo
IPC分类号： G06F3/14 , G06F13/16 , G09G1/16 , G09G5/00 , G09G5/36
CPC分类号： G06F13/1605 , G06F3/14 , G09G3/003 , G09G5/001 , G09G5/363
摘要： A computer system having a core logic chipset that interconnects a processor(s), a system memory and peripheral device agents. The core logic chipset has a programmable memory access arbiter that may be programmed to optimize accesses by the computer system processor(s) and agents to the system memory for best computer system performance. The memory access arbiter may be programmed specifically for each system agent. An access count register may be incorporated into the core logic chipset wherein each system agent may be represented by a portion of the access count register. The values programmed into the portions of the access count register determine how many memory accesses the associated agent may take before another agent is granted a memory access, and how many cachelines may be transferred during a memory access.
摘要翻译：具有将处理器，系统存储器和外围设备代理器互连的核心逻辑芯片组的计算机系统。核心逻辑芯片组具有可编程存储器访问仲裁器，其可以被编程为优化计算机系统处理器和代理到系统存储器的访问以获得最佳计算机系统性能。存储器访问仲裁器可以针对每个系统代理进行编程。访问计数寄存器可以并入到核心逻辑芯片组中，其中每个系统代理可以由访问计数寄存器的一部分来表示。编程到访问计数寄存器的部分中的值确定在授予存储器访问的另一个代理程序之前，相关联的代理可以执行多少内存访问，以及在存储器访问期间可以传送多少个高速缓存行。

16. 发明授权

US5999743A System and method for dynamically allocating accelerated graphics port memory space 失效
标题翻译：用于动态分配加速图形端口存储空间的系统和方法
公开(公告)号：US5999743A
公开(公告)日：1999-12-07
申请号：US926422
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliot
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliot
IPC分类号： G06F3/14 , G09G5/36 , G09G5/39 , B06F13/00
CPC分类号： G06F3/14 , G09G5/363 , G09G2360/121
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. Contiguous virtual memory address space must be allocated for the AGP device within the addressable memory space of the computer system, typically 4 gigabytes using 32 bit addressing. The required amount of virtual memory address space for AGP is determined from the AGP device and the information is put into a register of the core logic so that the computer system software may allocate the required amount of memory and assign a base address thereto during computer system startup or POST.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。必须为计算机系统的可寻址存储空间内的AGP设备分配连续的虚拟内存地址空间，通常使用32位寻址4 GB。从AGP设备确定AGP所需的虚拟内存地址空间量，并将信息放入核心逻辑的寄存器，以便计算机系统软件可以在计算机系统中分配所需量的存储器并分配基地址启动或POST。

17. 发明授权

US5999198A Graphics address remapping table entry feature flags for customizing the operation of memory pages associated with an accelerated graphics port device 失效
标题翻译：图形地址重映射表条目功能标志，用于自定义与加速图形端口设备关联的内存页面的操作
公开(公告)号：US5999198A
公开(公告)日：1999-12-07
申请号：US925772
申请日：1997-09-09
申请人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
发明人： Ronald T. Horan , Phillip M. Jones , Gregory N. Santos , Robert Allan Lester , Robert C. Elliott
IPC分类号： G06F3/14 , G06F12/08 , G09G5/393 , G06F15/16
CPC分类号： G06F3/14 , G06F12/0875 , G09G5/393 , G09G2360/121
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as a graphics controller, and a host processor and computer system memory wherein a Graphics Address Remapping Table ("GART table") is used by the core logic chipset to remap virtual memory addresses used by the AGP graphics controller into physical memory addresses that reside in the computer system memory. The GART table enables the AGP graphics controller to work in contiguous virtual memory address space, but actually use non-contiguous blocks or pages of physical system memory to store textures, command lists and the like. The GART table is made up of a plurality of entries, each entry comprising an address pointer to a base address of a memory page, and feature flags that may be used to customize the associated memory page.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为诸如图形控制器的加速图形端口（“AGP”）总线设备与主机处理器和计算机系统存储器之间的桥接，其中图形地址重映射表（“GART表” ）被核心逻辑芯片组用于将由AGP图形控制器使用的虚拟存储器地址重新映射到位于计算机系统存储器中的物理存储器地址。 GART表使AGP图形控制器能够在连续的虚拟内存地址空间中工作，但实际上使用不连续的物理系统内存块或页面来存储纹理，命令列表等。 GART表由多个条目组成，每个条目包括指向存储器页面的基址的地址指针，以及可用于定制关联的存储器页面的特征标志。

18. 发明授权

US5986677A Accelerated graphics port read transaction merging 失效
标题翻译：加速图形端口读取事务合并
公开(公告)号：US5986677A
公开(公告)日：1999-11-16
申请号：US941859
申请日：1997-09-30
申请人： Phillip M. Jones , Ronald T. Horan , Gregory N. Santos
发明人： Phillip M. Jones , Ronald T. Horan , Gregory N. Santos
IPC分类号： G06F13/16 , G06F13/14
CPC分类号： G06F13/1631
摘要： A computer system having a core logic chipset that functions as a bridge between an Accelerated Graphics Port ("AGP") bus device such as an AGP graphics controller, and a host processor and computer system memory wherein AGP transaction read requests are merged from the AGP graphics controller and retired when these requests are within a cacheline of the memory being accessed. The core logic chipset will request a memory cacheline read as it begins processing a current AGP transaction read request. Once the memory read access is initiated, the transaction read request will be popped off an AGP request queue in order to evaluate the next in order transaction request. If the next request can be partially or completely retired by the memory read access previously started, then the memory access that would have been normally required may be skipped and the data from the previous memory read access is used instead. This AGP read transaction merging may continue until the next in order transaction read request is located in a different cacheline of memory or the original memory request is ready to return data. A memory data buffer may also be utilized to store unused quadwords of the cacheline read from a memory access so that some subsequent AGP transaction requests may be retired without having to access a previously read cacheline of memory.
摘要翻译：具有核心逻辑芯片组的计算机系统，其作为AGP图形控制器之间的加速图形端口（“AGP”）总线装置与主机处理器之间的桥接，以及AGP事务读取请求从AGP合并的计算机系统存储器图形控制器，并且当这些请求在被访问的存储器的高速缓存行内时退出。核心逻辑芯片组将在开始处理当前的AGP事务读取请求时请求存储器高速缓存行读取。一旦启动了存储器读取访问，事务读取请求将从AGP请求队列中弹出，以便按顺序对事务请求进行评估。如果下一个请求可以被先前启动的存储器读取访问部分地或完全地退出，则可以跳过通常需要的存储器访问，而是使用来自先前的存储器读取访问的数据。该AGP读取事务合并可以继续，直到顺序事务读取请求位于存储器的不同高速缓存行中，或者原始存储器请求准备好返回数据。存储器数据缓冲器还可以用于存储从存储器访问读取的高速缓存行的未使用的四字，使得一些后续的AGP事务请求可以被停止，而不必访问先前读取的存储器的高速缓存行。

19. 发明授权

US5864688A Apparatus and method for positively and subtractively decoding addresses on a bus 失效
标题翻译：用于对总线上的地址进行正负的解码的装置和方法
公开(公告)号：US5864688A
公开(公告)日：1999-01-26
申请号：US684584
申请日：1996-07-19
申请人： Gregory N. Santos , David J. Maguire , Dwight D. Riley , James R. Edwards
发明人： Gregory N. Santos , David J. Maguire , Dwight D. Riley , James R. Edwards
IPC分类号： G06F13/36 , G06F13/40 , G06F12/00
CPC分类号： G06F13/4045
摘要： A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.
摘要翻译：具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。该桥包括用于控制解码的内部设备和配置寄存器。用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。根据对接状态，由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

20. 发明授权

US5781748A Computer system utilizing two ISA busses coupled to a mezzanine bus 失效
标题翻译：利用耦合到夹层总线的两条ISA总线的计算机系统
公开(公告)号：US5781748A
公开(公告)日：1998-07-14
申请号：US671316
申请日：1996-07-19
申请人： Gregory N. Santos , David J. Maguire , Dwight D. Riley , James R. Edwards
发明人： Gregory N. Santos , David J. Maguire , Dwight D. Riley , James R. Edwards
IPC分类号： G06F13/40 , H01J13/00
CPC分类号： G06F13/4027
摘要： A computer system having an expansion base for docking a portable portion of the computer system includes a bridge circuit for adaptively decoding addresses on a bus based on the docking status. Both the expansion base and the portable portion include the bridge circuit for passing cycles from a peripheral component interconnect (PCI) bus to an industry standard architecture (ISA) bus. The bridge includes internal devices and configuration registers for controlling the decoding. Bus cycles intended for internal devices and external devices connected to each respective ISA bus of the bridge circuits are positively decoded. Cycles not positively decoded and claimed are subtractively decoded by one of the bridge circuits depending on the docking status.
摘要翻译：具有用于对接计算机系统的便携式部分的扩展基座的计算机系统包括用于基于对接状态自适应地解码总线上的地址的桥接电路。扩展基座和便携式部分都包括用于将周期从外围部件互连（PCI）总线传递到工业标准架构（ISA）总线的桥接电路。该桥包括用于控制解码的内部设备和配置寄存器。用于连接到桥接电路的每个相应ISA总线的内部设备和外部设备的总线周期被正确解码。根据对接状态，由桥接电路之一对其中一个电路进行正确解码和声明的循环进行减法解码。

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