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11. 发明申请

US20090150555A1 MEMORY TO MEMORY COMMUNICATION AND STORAGE FOR HYBRID SYSTEMS 有权
标题翻译：对混合系统的记忆体通信和存储的记忆
公开(公告)号：US20090150555A1
公开(公告)日：2009-06-11
申请号：US11951709
申请日：2007-12-06
申请人： Moon J. Kim , Rajaram B. krishnamurthy , James R. Moulic
发明人： Moon J. Kim , Rajaram B. krishnamurthy , James R. Moulic
IPC分类号： G06F15/16
CPC分类号： H04L67/1097 , G06F3/0605 , G06F3/0638 , G06F3/064 , G06F3/067
摘要： The present invention relates to memory to memory communication and storage for hybrid systems. Under the present invention, a data stream is received on a first computing device of a hybrid system. An attempt is made to store the data stream on the first computing device up to a per stream limit and a total storage limit of the first computing device. It is then determined whether to store at least a portion of the data stream on a second computing device of the hybrid system that is in communication with the first computing device. This decision is based on the per stream limit and the total storage limit of the first computing device as well as a per stream limit and a total storage limit of the second computing device. Thereafter, the at least a portion of the data stream and a control signal are communicated to the second computing device for storage.
摘要翻译：本发明涉及用于混合系统的存储器到存储器通信和存储。在本发明中，在混合系统的第一计算设备上接收数据流。尝试将数据流存储在第一计算设备上，直到第一计算设备的每流限制和总存储限制。然后确定是否将数据流的至少一部分存储在与第一计算设备通信的混合系统的第二计算设备上。该决定基于第一计算设备的每流限制和总存储限制以及第二计算设备的每流限制和总存储限制。此后，数据流的至少一部分和控制信号被传送到第二计算设备以进行存储。

12. 发明申请

US20080181471A1 UNIVERSAL IMAGE PROCESSING 有权
标题翻译：通用图像处理
公开(公告)号：US20080181471A1
公开(公告)日：2008-07-31
申请号：US11668875
申请日：2007-01-30
申请人： William Hyun-Kee Chung , Bruce A. Foster , Moon J. Kim , James R. Moulic
发明人： William Hyun-Kee Chung , Bruce A. Foster , Moon J. Kim , James R. Moulic
IPC分类号： G06K9/00
CPC分类号： G06T1/00 , A61B6/463 , A61B6/464 , A61B6/5247 , A61B6/563 , G06F19/00 , G06F19/321 , G06T7/00 , G06T11/003
摘要： The present invention provides a universal and centralized image (e.g., medical, bio-molecular, etc.) processing system platform. The invention permits sharing both computation and visualization across a single universal platform, thus allowing for sharing of computing resources and visualization of images on a variety of imaging (client) devices without high-performance graphical display cards. In a typical embodiment a (e.g., medical) image 2D linear registration algorithm is implemented on a Cell Broadband Engine processor, which has nine processor cores on a chip and has a 4-way SIMD unit for each core.
摘要翻译：本发明提供了一种通用且集中的图像（例如医疗，生物分子等）处理系统平台。本发明允许在单个通用平台上共享计算和可视化，从而允许在不具有高性能图形显示卡的各种成像（客户端）设备上共享计算资源和可视化图像。在典型的实施例中，在Cell Broadband Engine处理器上实现（例如，医学）图像2D线性注册算法，该处理器在芯片上具有九个处理器核心，并且具有用于每个核心的4路SIMD单元。

13. 发明授权

US08331737B2 Heterogeneous image processing system 有权
标题翻译：异构图像处理系统
公开(公告)号：US08331737B2
公开(公告)日：2012-12-11
申请号：US11738711
申请日：2007-04-23
申请人： William H. Chung , Moon J. Kim , James R. Moulic , Toshiyuki Sanuki
发明人： William H. Chung , Moon J. Kim , James R. Moulic , Toshiyuki Sanuki
IPC分类号： G06K9/60
CPC分类号： G06T1/20
摘要： The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a multi-core processor system. To this extent, a multi-core processor system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications referred to herein as an image co-processor that comprises (among other things) a plurality of multi-core processors (MCPs) that work to process multiple images in an accelerated fashion.
摘要翻译：本发明涉及机器视觉计算环境，更具体地涉及一种用于使用多核处理器系统选择性地加速图像处理应用的执行的系统和方法。在这种情况下，多核处理器系统通常被定义为多平台的，并且可能通过网络或其他连接分布。本发明提供了一种用于执行图像处理应用的机器视觉系统和方法，这里称为图像协处理器，其包括（尤其是）多个多核处理器（MCP），其工作以加速方式处理多个图像。

14. 发明授权

US08326092B2 Heterogeneous image processing system 有权
标题翻译：异构图像处理系统
公开(公告)号：US08326092B2
公开(公告)日：2012-12-04
申请号：US11738723
申请日：2007-04-23
申请人： William H. Chung , Moon J. Kim , James R. Moulic , Toshiyuki Sanuki
发明人： William H. Chung , Moon J. Kim , James R. Moulic , Toshiyuki Sanuki
IPC分类号： G06K9/60
CPC分类号： G06T1/20
摘要： The present invention relates to machine vision computing environments, and more specifically relates to a system and method for selectively accelerating the execution of image processing applications using a hybrid computing system. To this extent, a hybrid system is generally defined as one that is multi-platform, and potentially distributed via a network or other connection. The invention provides a machine vision system and method for executing image processing applications on a hybrid image processing system referred to herein as an image co-processor that comprises (among other things) a plurality of special purpose engines (SPEs) that work to process multiple images in an accelerated fashion.
摘要翻译：本发明涉及机器视觉计算环境，更具体地涉及一种用于使用混合计算系统选择性地加速图像处理应用的执行的系统和方法。在这种程度上，混合系统通常被定义为多平台的，并且可能通过网络或其他连接分发。本发明提供了一种用于在这里称为图像协处理器的混合图像处理系统上执行图像处理应用的机器视觉系统和方法，该图像协处理器包括（尤其是）多个专用引擎（SPE），其用于处理多个图像以加速的方式。

15. 发明申请

US20090138748A1 APPARATUS AND METHOD FOR MICRO PERFORMANCE TUNING OF A CLOCKED DIGITAL SYSTEM 失效
标题翻译：一种时钟数字系统的微观性能调谐的装置和方法
公开(公告)号：US20090138748A1
公开(公告)日：2009-05-28
申请号：US11946466
申请日：2007-11-28
申请人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Daeik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F1/08
CPC分类号： G06F1/08
摘要： An apparatus and method for micro-tuning an effective clock frequency of a core in a microprocessor. The apparatus includes a microprocessor having at least one core with logic configured to transition between states, a clock signal coupled to the microprocessor, the clock signal having a predetermined clock frequency based on a worst-case clock frequency and a predetermined clock period. The apparatus further including at least one voltage drop sensor coupled to the core, the sensor being configured to generate an output signal for detecting a voltage drop in the core and to determine whether or not the output signal is detected within the clock period and, if the output signal is not detected, the sensor dynamically adjusts the clock period of the clock signal provided to the core to allow more time to complete state transitions, such that, dynamically adjusting the clock period effectively changes an effective core clock frequency.
摘要翻译：一种用于微调微处理器中的核心的有效时钟频率的装置和方法。该装置包括具有至少一个具有逻辑的核心的微处理器，其配置成在状态之间转换，耦合到微处理器的时钟信号，时钟信号具有基于最坏情况时钟频率和预定时钟周期的预定时钟频率。所述装置还包括耦合到所述芯的至少一个电压降传感器，所述传感器被配置为产生用于检测所述磁芯中的电压降的输出信号，并且确定在所述时钟周期内是否检测到所述输出信号，以及如果输出信号未检测到，传感器动态地调整提供给核心的时钟信号的时钟周期，以允许更多的时间完成状态转换，使得动态调整时钟周期有效地改变有效的核心时钟频率。

16. 发明申请

US20080177506A1 METHOD AND SYSTEM FOR TESTING PROCESSOR CORES 有权
标题翻译：用于测试加工器的方法和系统
公开(公告)号：US20080177506A1
公开(公告)日：2008-07-24
申请号：US11624329
申请日：2007-01-18
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

17. 发明授权

US09332074B2 Memory to memory communication and storage for hybrid systems 有权
标题翻译：用于混合系统的内存到内存通信和存储
公开(公告)号：US09332074B2
公开(公告)日：2016-05-03
申请号：US11951709
申请日：2007-12-06
申请人： Moon J. Kim , Rajaram B. Krishnamurthy , James R. Moulic
发明人： Moon J. Kim , Rajaram B. Krishnamurthy , James R. Moulic
IPC分类号： G06F15/16 , G06F12/00 , H04L29/08 , G06F3/06
CPC分类号： H04L67/1097 , G06F3/0605 , G06F3/0638 , G06F3/064 , G06F3/067
摘要： The present invention relates to memory to memory communication and storage for hybrid systems. Under the present invention, a data stream is received on a first computing device of a hybrid system. An attempt is made to store the data stream on the first computing device up to a per stream limit and a total storage limit of the first computing device. It is then determined whether to store at least a portion of the data stream on a second computing device of the hybrid system that is in communication with the first computing device. This decision is based on the per stream limit and the total storage limit of the first computing device as well as a per stream limit and a total storage limit of the second computing device. Thereafter, the at least a portion of the data stream and a control signal are communicated to the second computing device for storage.
摘要翻译：本发明涉及用于混合系统的存储器到存储器通信和存储。在本发明中，在混合系统的第一计算设备上接收数据流。尝试将数据流存储在第一计算设备上，直到第一计算设备的每流限制和总存储限制。然后确定是否将数据流的至少一部分存储在与第一计算设备通信的混合系统的第二计算设备上。该决定基于第一计算设备的每流限制和总存储限制以及第二计算设备的每流限制和总存储限制。此后，数据流的至少一部分和控制信号被传送到第二计算设备以进行存储。

18. 发明授权

US09135073B2 Server-processor hybrid system for processing data 有权
标题翻译：用于处理数据的服务器处理器混合系统
公开(公告)号：US09135073B2
公开(公告)日：2015-09-15
申请号：US11940506
申请日：2007-11-15
申请人： Moon J. Kim , Rajaram B. Krishnamurthy , James R. Moulic
发明人： Moon J. Kim , Rajaram B. Krishnamurthy , James R. Moulic
IPC分类号： G06F15/16 , G06F9/50 , G06F11/07
CPC分类号： H04L67/10 , G06F9/50 , G06F9/5005 , G06F9/5044 , G06F11/0709 , G06F2209/509 , H04L67/02 , H04L67/16
摘要： The present invention relates to a server-processor hybrid system that comprises (among other things) a set (one or more) of front-end servers (e.g., mainframes) and a set of back-end application optimized processors. Moreover, implementations of the invention provide a server and processor hybrid system and method for distributing and managing the execution of applications at a fine-grained level via an I/O-connected hybrid system. This method allows one system to be used to manage and control the system functions, and one or more other systems to co-processor.
摘要翻译：本发明涉及一种服务器 - 处理器混合系统，其包括（其中包括）一组（一个或多个）前端服务器（例如，大型机）和一组后端应用优化处理器。此外，本发明的实现提供了一种服务器和处理器混合系统和方法，用于经由I / O连接的混合系统在细粒度级别上分发和管理应用的执行。该方法允许一个系统用于管理和控制系统功能，以及一个或多个其他系统协同处理器。

19. 发明授权

US07876940B2 Universal image processing 有权
标题翻译：通用图像处理
公开(公告)号：US07876940B2
公开(公告)日：2011-01-25
申请号：US11668875
申请日：2007-01-30
申请人： William Hyun-Kee Chung , Bruce A. Foster , Moon J. Kim , James R. Moulic
发明人： William Hyun-Kee Chung , Bruce A. Foster , Moon J. Kim , James R. Moulic
IPC分类号： G06K9/00
CPC分类号： G06T1/00 , A61B6/463 , A61B6/464 , A61B6/5247 , A61B6/563 , G06F19/00 , G06F19/321 , G06T7/00 , G06T11/003
摘要： The present invention provides a universal and centralized image (e.g., medical, bio-molecular, etc.) processing system platform. The invention permits sharing both computation and visualization across a single universal platform, thus allowing for sharing of computing resources and visualization of images on a variety of imaging (client) devices without high-performance graphical display cards. In a typical embodiment a (e.g., medical) image 2D linear registration algorithm is implemented on a Cell Broadband Engine processor, which has nine processor cores on a chip and has a 4-way SIMD unit for each core.
摘要翻译：本发明提供了一种通用且集中的图像（例如医疗，生物分子等）处理系统平台。本发明允许在单个通用平台上共享计算和可视化，从而允许在不具有高性能图形显示卡的各种成像（客户端）设备上共享计算资源和可视化图像。在典型的实施例中，在Cell Broadband Engine处理器上实现（例如，医学）图像2D线性注册算法，该处理器在芯片上具有九个处理器核心，并且具有用于每个核心的4路SIMD单元。

20. 发明申请

US20080262777A1 SYSTEM FOR TESTING PROCESSOR CORES 有权
标题翻译：测试加工器系统
公开(公告)号：US20080262777A1
公开(公告)日：2008-10-23
申请号：US12128075
申请日：2008-05-28
申请人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
发明人： Dae Ik Kim , Jonghae Kim , Moon J. Kim , James R. Moulic
IPC分类号： G01R31/00 , G06F15/00
CPC分类号： G06F11/24 , G01R31/3004 , G01R31/31721 , G01R31/318505
摘要： Systems, methods and program codes are provided for testing multi-core processor chip structures. Individual processor core power supply voltages are provided through controlling individual power supplies for each core, in one aspect to ensure that one or more cores operate at clock rates in compliance with one or more performance specifications. In one example, a first power supply voltage supplied to a first processing core differs from a second core power supply voltage supplied to a second processing core, both cores operating in compliance with a reference clock rate specification. Core power supply voltages may be selected from ordered discrete supply voltages derived by progressively raising or lowering a first supply voltage, optionally wherein the selected supply voltage also enables the core to operate within another performance specification.
摘要翻译：提供了系统，方法和程序代码，用于测试多核处理器芯片结构。单个处理器核心电源电压通过控制每个核心的单独电源来提供，在一个方面，以确保一个或多个核心以按照一个或多个性能规格的时钟速率运行。在一个示例中，提供给第一处理核心的第一电源电压与提供给第二处理核心的第二核心电源电压不同，两个核心都遵循参考时钟速率规范操作。核心电源电压可以从通过逐渐提高或降低第一电源电压而导出的有序离散电源电压中选择，任选地，其中所选择的电源电压还使得核能够在另一性能规格内操作。

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