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11. 发明授权

US07301219B2 Electrically erasable programmable read only memory (EEPROM) cell and method for making the same 有权
标题翻译：电可擦除可编程只读存储器（EEPROM）单元及其制作方法
公开(公告)号：US07301219B2
公开(公告)日：2007-11-27
申请号：US11146777
申请日：2005-06-06
申请人： Tzu-Hsuan Hsu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Tzu-Hsuan Hsu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： H01L29/00 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/7885 , H01L29/7887 , H01L29/7923 , Y10S257/90
摘要： An asymmetrically doped memory cell has first and second N+ doped junctions on a P substrate. A composite charge trapping layer is disposed over the P substrate and between the first and the second N+ doped junctions. A N− doped region is positioned adjacent to the first N+ doped junction and under the composite charge trapping layer. A P− doped region is positioned adjacent to the second N+ doped junction and under the composite charge trapping layer. The asymmetrically doped memory cell will store charges at the end of the composite charge trapping layer that is above the P− doped region. The asymmetrically doped memory cell can function as an electrically erasable programmable read only memory cell, and is capable of multiple level cell operations. A method for making an asymmetrically doped memory cell is also described.
摘要翻译：不对称掺杂的存储单元在P衬底上具有第一和第二N +掺杂结。复合电荷捕获层设置在P衬底上并且在第一和第二N +掺杂结之间。 N掺杂区域邻近第一N +掺杂结并位于复合电荷俘获层下方。 P-掺杂区域邻近第二N +掺杂结并位于复合电荷俘获层下方。非对称掺杂的存储单元将在复合电荷捕获层的末端在P掺杂区域之上存储电荷。非对称掺杂的存储单元可以用作电可擦除可编程只读存储器单元，并且能够进行多级单元操作。还描述了制造非对称掺杂的存储单元的方法。

12. 发明授权

US07209390B2 Operation scheme for spectrum shift in charge trapping non-volatile memory 有权
标题翻译：电荷捕获非易失性存储器频谱移位操作方案
公开(公告)号：US07209390B2
公开(公告)日：2007-04-24
申请号：US10876378
申请日：2004-06-24
申请人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
发明人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： G11C16/00
CPC分类号： G11C16/3481 , G11C16/0466 , G11C16/3436
摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles. The charge retention properties can be greatly improved by these refill cycles.
摘要翻译：具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。通过这些再填充循环可以大大提高电荷保持性。

13. 发明申请

US20050237816A1 Operation scheme for spectrum shift in charge trapping non-volatile memory 有权
标题翻译：电荷捕获非易失性存储器频谱移位操作方案
公开(公告)号：US20050237816A1
公开(公告)日：2005-10-27
申请号：US10876378
申请日：2004-06-24
申请人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
发明人： Hang-Ting Lue , Yen-Hao Shih , Kuang Yeu Hsieh , Ming-Hsiu Lee , Chao-I Wu , Tzu-Hsuan Hsu
IPC分类号： G11C11/36 , G11C16/04 , G11C16/34
CPC分类号： G11C16/3481 , G11C16/0466 , G11C16/3436
摘要： A memory cell with a charge trapping structure is programmed using refill cycles that include a program pulse followed by a charge balancing pulse that causes ejection of electrons from the charge trapping structure. The refill cycle causes a blue spectrum shift in the charge trap distribution in the charge trapping structure. The algorithm includes program verify operations after the program pulse, and completes when a successful program verify operation occurs after a number of refill cycles.
摘要翻译：具有电荷俘获结构的存储单元使用包括编程脉冲，随后是电荷平衡脉冲的再填充循环被编程，该电荷平衡脉冲引起电荷从电荷捕获结构的喷出。充电周期引起电荷捕获结构中电荷陷阱分布的蓝色光谱偏移。该算法包括在程序脉冲之后的程序验证操作，并且在多个填充循环之后发生成功的程序验证操作时完成。

14. 发明授权

US09019771B2 Dielectric charge trapping memory cells with redundancy 有权
标题翻译：介质电荷捕获具有冗余的存储单元
公开(公告)号：US09019771B2
公开(公告)日：2015-04-28
申请号：US13661723
申请日：2012-10-26
申请人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee
发明人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee
IPC分类号： G11C16/06 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0475 , G11C16/10
摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.
摘要翻译：介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

15. 发明授权

US08426294B2 3D memory array arranged for FN tunneling program and erase 有权
标题翻译： 3D存储阵列用于FN隧道编程和擦除
公开(公告)号：US08426294B2
公开(公告)日：2013-04-23
申请号：US13476964
申请日：2012-05-21
申请人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Hang-Ting Lue
发明人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Hang-Ting Lue
IPC分类号： H01L29/76
CPC分类号： G11C16/0458 , H01L27/0688 , H01L27/10 , H01L27/11578 , H01L27/11582
摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。该设备可以作为3D和解码的闪存操作。

16. 发明申请

US20120170359A1 Phase Change Memory With Fast Write Characteristics 有权
标题翻译：具有快写特性的相变存储器
公开(公告)号：US20120170359A1
公开(公告)日：2012-07-05
申请号：US12985253
申请日：2011-01-05
申请人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
发明人： Chao-I Wu , Yen-Hao Shih , Ming-Hsiu Lee
IPC分类号： G11C11/00 , H01L21/02
CPC分类号： H01L45/06 , G11C11/005 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C14/00 , G11C2013/0083 , G11C2013/0092 , H01L27/2463 , H01L45/1233 , H01L45/144 , H01L45/1625 , H01L45/1641
摘要： A memory device including programmable resistance memory cells, including electrically pre-stressed target memory cells. The pre-stressed target memory cells have one of a lower voltage transition threshold, a shorter duration set interval and a longer reset state retention characteristic. Biasing circuitry is included on the device configured to control the pre-stressing operations, and to apply read, set and reset operations that can be modified for the pre-stressed memory cells.
摘要翻译：一种包括可编程电阻存储单元的存储器件，包括电预应力目标存储单元。预应力目标存储单元具有较低电压转变阈值，较短持续时间设定间隔和较长复位状态保持特性之一。设备上包括偏置电路，用于控制预应力操作，以及应用对预应力存储单元进行修改的读取，置位和复位操作。

17. 发明申请

US20110121411A1 THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING AND OPERATING THE SAME 有权
标题翻译：三维存储器件及其制造和操作方法
公开(公告)号：US20110121411A1
公开(公告)日：2011-05-26
申请号：US13022588
申请日：2011-02-07
申请人： Ming-Hsiu Lee , Yen-Hao Shih
发明人： Ming-Hsiu Lee , Yen-Hao Shih
IPC分类号： H01L29/78
CPC分类号： G11C13/0023 , G11C13/00 , G11C13/0004 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： The invention provides a semiconductor cell comprising a gate, a dielectric layer, a channel layer, a source region, a drain region and an oxide region. The dielectric layer is adjacent to the gate. The channel layer is adjacent to the dielectric layer and is formed above a source region, a drain region, and an oxide region.
摘要翻译：本发明提供一种包括栅极，电介质层，沟道层，源极区，漏极区和氧化物区的半导体元件。电介质层与栅极相邻。沟道层与电介质层相邻并且形成在源极区，漏极区和氧化物区的上方。

18. 发明申请

US20090231942A1 THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING AND OPERATING THE SAME 有权
标题翻译：三维存储器件及其制造和操作方法
公开(公告)号：US20090231942A1
公开(公告)日：2009-09-17
申请号：US12471411
申请日：2009-05-25
申请人： Ming-Hsiu Lee , Yen-Hao Shih
发明人： Ming-Hsiu Lee , Yen-Hao Shih
IPC分类号： G11C8/00 , G11C5/06
CPC分类号： G11C13/0023 , G11C13/00 , G11C13/0004 , G11C17/06 , G11C17/16 , G11C2213/71 , G11C2213/77 , H01L21/84 , H01L27/0688 , H01L27/115 , H01L27/11568 , H01L27/11578 , H01L27/1203 , H01L29/66833 , H01L29/792
摘要： A method of accessing memory cells is disclosed. A first signal is sent to at least one layer select transistor. The at least one layer select transistor is activated based on the first signal. Signals are communicated to or from one or more memory cells based on the activated at least layer select transistor.
摘要翻译：公开了访问存储器单元的方法。第一信号被发送到至少一个层选择晶体管。基于第一信号激活至少一个层选择晶体管。基于激活的至少层选择晶体管将信号传送到或来自一个或多个存储器单元。

19. 发明授权

US09035275B2 Three dimensional memory array adjacent to trench sidewalls 有权
标题翻译：与沟槽侧壁相邻的三维存储器阵列
公开(公告)号：US09035275B2
公开(公告)日：2015-05-19
申请号：US13330525
申请日：2011-12-19
申请人： Wei-Chih Chien , Ming-Hsiu Lee , Shih-Hung Chen
发明人： Wei-Chih Chien , Ming-Hsiu Lee , Shih-Hung Chen
IPC分类号： H01L29/06 , H01L27/24 , H01L45/00
CPC分类号： H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/1226 , H01L45/146 , H01L45/147 , H01L45/1633
摘要： A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.
摘要翻译：一种自对准堆叠式存储单元阵列结构及其制造方法。存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。

20. 发明申请

US20110069538A1 MULTI-LEVEL CELL PROGRAMMING OF PCM BY VARYING THE RESET AMPLITUDE 失效
标题翻译：通过改变复位电压，PCM的多级电容编程
公开(公告)号：US20110069538A1
公开(公告)日：2011-03-24
申请号：US12564904
申请日：2009-09-22
申请人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
发明人： Chung H. Lam , Ming-Hsiu Lee , Thomas Nirschi , Bipin Rajendran
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C11/5678 , G11C13/0069 , G11C2013/0083 , G11C2013/0092
摘要： A phase change memory device and a method for programming the same. The method includes determining a characterized lowest SET current and corresponding SET resistance for the phase change memory device. The method includes determining a characterized RESET current slope for the phase change memory device. The method also includes calculating a first current amplitude for a RESET pulse based on the characterized lowest SET current and the characterized RESET current slope. The method includes applying the RESET pulse to a target memory cell in the phase change memory device and measuring the resistance of the target memory cell. If the measured resistance is substantially less than a target resistance, the method further includes applying one or more additional RESET pulses. In one embodiment of the invention, the one or more additional RESET pulses have current amplitudes greater than a previously applied RESET pulse.
摘要翻译：相变存储器件及其编程方法。该方法包括确定用于相变存储器件的特征最低的SET电流和相应的SET电阻。该方法包括确定用于相变存储器件的特征化的RESET电流斜率。该方法还包括基于所表征的最低SET电流和表征的RESET电流斜率来计算RESET脉冲的第一电流幅度。该方法包括将RESET脉冲施加到相变存储器件中的目标存储单元并测量目标存储单元的电阻。如果所测量的电阻远小于目标电阻，该方法还包括应用一个或多个附加的RESET脉冲。在本发明的一个实施例中，一个或多个附加的RESET脉冲的电流幅度大于先前施加的RESET脉冲。

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