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11. 发明申请

US20100221851A1 TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING 有权
标题翻译：用于检测半导体加工过程中充电效应的测试结构和方法
公开(公告)号：US20100221851A1
公开(公告)日：2010-09-02
申请号：US12777858
申请日：2010-05-11
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

12. 发明授权

US07209385B1 Array structure for assisted-charge memory devices 有权
标题翻译：辅助电荷存储器件的阵列结构
公开(公告)号：US07209385B1
公开(公告)日：2007-04-24
申请号：US11327561
申请日：2006-01-06
申请人： Chao-I Wu , Ming Hsiu Lee , Ming-Chang Kuo
发明人： Chao-I Wu , Ming Hsiu Lee , Ming-Chang Kuo
IPC分类号： G11C16/04
CPC分类号： G11C16/0491 , G11C16/0466 , G11C16/14 , H01L21/28282 , H01L29/792
摘要： An Assisted Charge (AC) Memory cell comprises a transistor that includes, for example, a p-type substrate with an n+ source region and an n+ drain region implanted on the p-type substrate. A gate electrode can be formed over the substrate and portions of the source and drain regions. The gate electrode can comprise a trapping structure. The trapping structure can be treated as electrically split into two sides. One side can be referred to as the “AC-side” and can be fixed at a high voltage by trapping electrons within the structure. The electrons are referred to as assisted charges. The other side of can be used to store data and is referred to as the “data-side.” The abrupt electric field between AC-side and the data-side can enhance programming efficiency.
摘要翻译：辅助充电（AC）存储单元包括晶体管，其包括例如p型衬底，其具有n +源极区域和n +漏极区域注入在p型衬底上。栅电极可以形成在衬底上以及源区和漏区的部分之上。栅电极可以包括捕获结构。捕获结构可以被电分为两侧。一侧可以称为“AC侧”，并且可以通过在结构内捕获电子而将其固定在高电压。电子被称为辅助电荷。另一边可以用来存储数据，被称为“数据端”。 AC侧和数据侧之间的突发电场可以提高编程效率。

13. 发明授权

US07787294B2 Operating method of memory 有权
标题翻译：记忆的操作方法
公开(公告)号：US07787294B2
公开(公告)日：2010-08-31
申请号：US12031189
申请日：2008-02-14
申请人： Ming-Chang Kuo , Ming-Hsiu Lee
发明人： Ming-Chang Kuo , Ming-Hsiu Lee
IPC分类号： G11C16/04
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0491
摘要： An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.
摘要翻译：提供了一种存储器的操作方法。存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。在编程存储器期间，选择一列存储单元。在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

14. 发明申请

US20090207656A1 OPERATING METHOD OF MEMORY 有权
标题翻译：存储器的操作方法
公开(公告)号：US20090207656A1
公开(公告)日：2009-08-20
申请号：US12031189
申请日：2008-02-14
申请人： Ming-Chang Kuo , Ming-Hsiu Lee
发明人： Ming-Chang Kuo , Ming-Hsiu Lee
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0491
摘要： An operating method of a memory is provided. The memory includes a memory cell array composed of a plurality of memory cells, a plurality of bit lines, and a plurality of word lines. During programming the memory, a column of memory cells is selected. A voltage difference is respectively occurred between a bit line corresponding to first source/drain regions of the memory cells in the selected column and adjacent two bit lines, and a bias is respectively applied to a word line corresponding to a control gate of each memory cell in the selected column so as to allow a data bit of the memory cell at a plurality of predetermined programmed states and an unusable bit of each memory cell in an adjacent column which shares the same bit line with the selected column at an unusable state.
摘要翻译：提供了一种存储器的操作方法。存储器包括由多个存储单元，多个位线和多个字线组成的存储单元阵列。在编程存储器期间，选择一列存储单元。在对应于所选列的存储单元的第一源极/漏极区域和相邻的两个位线的位线之间分别产生电压差，偏置分别施加到与每个存储单元的控制栅极相对应的字线在所选择的列中，以允许存储器单元的数据位处于多个预定编程状态，并且在相邻列中的每个存储器单元的不可用位与所选择的列共享与不可用状态相同的位线。

15. 发明申请

US20070236237A1 A TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING USING A DELAYED INVERSION POINT TECHNIQUE 有权
标题翻译：使用延迟反转点技术在半导体处理期间检测充电效应的测试结构和方法
公开(公告)号：US20070236237A1
公开(公告)日：2007-10-11
申请号：US11279224
申请日：2006-04-10
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-l Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-l Wu
IPC分类号： G01R31/26
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.
摘要翻译：半导体工艺测试结构包括栅电极，电荷捕获层和扩散区。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用CV测量来检测是否发生了Vfb偏移。如果处理步骤导致电荷效应，则感应电荷将不均匀。如果测试结构的充电不均匀，则不会有Vfb偏移。然后可以使用延迟反转点技术来监视充电状态。

16. 发明授权

US07474562B2 Method of forming and operating an assisted charge memory device 有权
标题翻译：形成和操作辅助电荷存储器件的方法
公开(公告)号：US07474562B2
公开(公告)日：2009-01-06
申请号：US11292024
申请日：2005-12-01
申请人： Ming-Chang Kuo , Chao-I Wu , Ming-Hsin Lee , Tzu-Hsuan Hsu
发明人： Ming-Chang Kuo , Chao-I Wu , Ming-Hsin Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0466 , H01L21/28282 , H01L29/42332 , H01L29/7887 , H01L29/7923
摘要： A method is provided of forming an assisted charge memory (AC-memory) cell. The method uses a two-sided charge trap memory cell that includes a two-sided charge trapping layer. A charge is formed in at least a portion of the two-sided charge trapping layer. One side (AC-side) of the two-sided charge trapping layer always has a fixed high threshold voltage (Vt) level which is the assisted charge for the AC-memory cell. The other side (data-side) is used for memory operations.
摘要翻译：提供了形成辅助电荷存储器（AC-存储器）单元的方法。该方法使用包括双面电荷捕获层的双面电荷陷阱存储单元。在双面电荷俘获层的至少一部分中形成电荷。双面电荷捕获层的一侧（AC侧）总是具有固定的高阈值电压（Vt）电平，其为AC存储单元的辅助电荷。另一方（数据端）用于存储器操作。

17. 发明申请

US20070267677A1 SINGLE POLY NON-VOLATILE MEMORY DEVICE WITH INVERSION DIFFUSION REGIONS AND METHODS FOR OPERATING THE SAME 有权
标题翻译：具有反向扩散区域的单个聚合非挥发性存储器件及其操作方法
公开(公告)号：US20070267677A1
公开(公告)日：2007-11-22
申请号：US11383924
申请日：2006-05-17
申请人： Ming-Chang Kuo , Chao-I Wu
发明人： Ming-Chang Kuo , Chao-I Wu
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , G11C16/0433 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/66825
摘要： A non-volatile memory device comprises a substrate with the dielectric layer formed thereon. A control gate and a floating gate are then formed on top of the dielectric layer. Accordingly, a non-volatile memory device can be constructed using a single poly process that is compatible with conventional CMOS processes. In addition, an assist gate, or assist gates are formed on the dielectric layer next to and between the control gate and floating gate respectively. The assist gates are used to form inversion diffusion regions in the substrate. By using the assist gates to form inversion diffusion regions, the overall size of the device can be reduced, which can improve device density.
摘要翻译：非易失性存储器件包括其上形成有电介质层的衬底。然后在电介质层的顶部形成控制栅极和浮置栅极。因此，可以使用与常规CMOS工艺兼容的单一多工艺来构造非易失性存储器件。此外，辅助栅极或辅助栅极分别形成在控制栅极和浮置栅极之间和之间的电介质层上。辅助栅极用于在衬底中形成反向扩散区域。通过使用辅助栅极形成反向扩散区域，可以减小器件的整体尺寸，这可以提高器件密度。

18. 发明申请

US20070232000A1 FABRICATING METHOD OF A NON-VOLATILE MEMORY 有权
标题翻译：非易失性存储器的制作方法
公开(公告)号：US20070232000A1
公开(公告)日：2007-10-04
申请号：US11760142
申请日：2007-06-08
申请人： Ming-Chang Kuo , Chao-I Wu
发明人： Ming-Chang Kuo , Chao-I Wu
IPC分类号： H01L21/336
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L29/42328 , H01L29/42344 , H01L29/7883 , H01L29/7885
摘要： A method of fabricating a non-volatile memory is provided. A stacked structure is formed over a substrate, and the stacked structure has a gate dielectric layer and a floating gate thereon. A first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed over the top and the sidewalls of the stacked structure and the exposed substrate. A charge storage layer covers over the top and sidewalls of the stacked structure. Also, a pair of auxiliary gates is formed over the substrate beside the charge storage layer, and a gap is between the auxiliary gates and the charge storage layer.
摘要翻译：提供了一种制造非易失性存储器的方法。堆叠结构形成在衬底上，堆叠结构在其上具有栅介电层和浮栅。第一电介质层，第二电介质层和第三电介质层分别形成在层叠结构的顶部和侧壁以及暴露的基板上。电荷存储层覆盖层叠结构的顶部和侧壁。此外，在电荷存储层旁边的基板上形成一对辅助栅极，并且在辅助栅极和电荷存储层之间形成间隙。

19. 发明申请

US20070212800A1 Methods for detecting charge effects during semiconductor processing 审中-公开
标题翻译：在半导体加工过程中检测电荷效应的方法
公开(公告)号：US20070212800A1
公开(公告)日：2007-09-13
申请号：US11370362
申请日：2006-03-08
申请人： Chao-I Wu , Ming Lee , Ming-Chang Kuo
发明人： Chao-I Wu , Ming Lee , Ming-Chang Kuo
IPC分类号： H01L21/66
CPC分类号： H01L22/14
摘要： A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A charge pump current can be used to detect the charging effect during various processing steps.
摘要翻译：半导体工艺测试结构包括栅电极，电荷捕获层和扩散区。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。可以使用电荷泵电流来检测各种处理步骤中的充电效果。

20. 发明授权

US08659952B2 Method of operating non-volatile memory 有权
标题翻译：操作非易失性存储器的方法
公开(公告)号：US08659952B2
公开(公告)日：2014-02-25
申请号：US12169142
申请日：2008-07-08
申请人： Ming-Chang Kuo , Chao-I Wu
发明人： Ming-Chang Kuo , Chao-I Wu
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0475 , G11C16/12
摘要： A method of operating a non-volatile memory having a substrate, a gate, a charge-trapping layer, a source region and a drain region is provided. The charge-trapping layer close to the source region is an auxiliary charge region and the charge-trapping layer close to the drain region is a data storage region. Before prosecuting the operation, electrons have been injected into the auxiliary charge region. When prosecuting the programming operation, a first voltage is applied to the gate, a second voltage is applied to the source region, a third voltage is applied to the drain region and a fourth voltage is applied to the substrate. The first voltage is greater than the fourth voltage, the third voltage is greater than the second voltage, and the second voltage is greater than the fourth voltage to initiate a channel initiated secondary hot electron injection to inject electrons into the data storage region.
摘要翻译：提供一种操作具有基板，栅极，电荷俘获层，源极区域和漏极区域的非易失性存储器的方法。靠近源区的电荷捕获层是辅助电荷区，靠近漏极区的电荷捕获层是数据存储区。在起诉前，电子注入到辅助电荷区域。当起动编程操作时，向栅极施加第一电压，将第二电压施加到源极区域，向漏极区域施加第三电压，并向衬底施加第四电压。第一电压大于第四电压，第三电压大于第二电压，第二电压大于第四电压，以启动通道启动的次级热电子注入以将电子注入数据存储区域。

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