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11. 发明申请

US20050101075A1 Method of forming a field effect transistors 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US20050101075A1
公开(公告)日：2005-05-12
申请号：US11000786
申请日：2004-11-30
申请人： Sanh Tang , Michael Violette , Robert Burke
发明人： Sanh Tang , Michael Violette , Robert Burke
IPC分类号： G06K19/07 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/3205
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

12. 发明申请

US20070105323A1 Method of forming a field effect transistor 审中-公开
标题翻译：形成场效应晶体管的方法
公开(公告)号：US20070105323A1
公开(公告)日：2007-05-10
申请号：US11643366
申请日：2006-12-20
申请人： Sanh Tang , Michael Violette , Robert Burke
发明人： Sanh Tang , Michael Violette , Robert Burke
IPC分类号： H01L21/336
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

13. 发明申请

US20050095767A1 METHODS OF FORMING FIELD EFFECT TRANSISTORS AND METHODS OF FORMING FIELD EFFECT TRANSISTOR GATES AND GATE LINES 有权
标题翻译：形成场效应晶体的方法及其形成场效应晶体管栅和栅极线的方法
公开(公告)号：US20050095767A1
公开(公告)日：2005-05-05
申请号：US11001145
申请日：2004-11-30
申请人： Sanh Tang , Michael Violette , Robert Burke
发明人： Sanh Tang , Michael Violette , Robert Burke
IPC分类号： G06K19/07 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/00 , H01L21/4763
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

14. 发明申请

US20050095756A1 Method of forming a field effect transistor 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US20050095756A1
公开(公告)日：2005-05-05
申请号：US11000588
申请日：2004-11-30
申请人： Sanh Tang , Michael Violette , Robert Burke
发明人： Sanh Tang , Michael Violette , Robert Burke
IPC分类号： G06K19/07 , H01L21/336 , H01L21/762 , H01L21/8234 , H01L21/00 , H01L21/84
CPC分类号： H01L29/7833 , G06K19/0723 , G06K19/0726 , G06K19/07771 , H01L21/76229 , H01L21/76232 , H01L21/76264 , H01L21/823418 , H01L21/823437 , H01L21/823481 , H01L21/823814 , H01L21/823828 , H01L29/1083 , H01L29/41783 , H01L29/66545 , H01L29/66583 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： In one implementation, a method of forming a field effect transistor includes etching an opening into source/drain area of a semiconductor substrate. The opening has a base comprising semiconductive material. After the etching, insulative material is formed within the opening over the semiconductive material base. The insulative material less than completely fills the opening and has a substantially uniform thickness across the opening. Semiconductive source/drain material is formed within the opening over the insulative material within the opening. A transistor gate is provided operatively proximate the semiconductive source/drain material. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，形成场效应晶体管的方法包括蚀刻半导体衬底的源/漏区的开口。开口具有包括半导体材料的基底。在蚀刻之后，在半导体材料基体的开口内形成绝缘材料。绝缘材料小于完全填充开口并且在开口上具有基本均匀的厚度。在开口内的绝缘材料的开口内形成半导电源极/漏极材料。半导体源极/漏极材料可操作地提供晶体管栅极。考虑了其他方面和实现。

15. 发明授权

US07402861B2 Memory cells and select gates of NAND memory arrays 有权
标题翻译： NAND存储器阵列的存储单元和选择门
公开(公告)号：US07402861B2
公开(公告)日：2008-07-22
申请号：US11215902
申请日：2005-08-31
申请人： Todd R. Abbott , Michael Violette
发明人： Todd R. Abbott , Michael Violette
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , H01L27/115
摘要： A select gate of a NAND memory array has a first dielectric layer formed on a semiconductor substrate. A first conductive layer is formed on the first dielectric layer. Conductive spacers are formed on sidewalls of the first conductive layer and are located between an upper surface of the first conductive layer and the first dielectric layer. A second dielectric layer overlies the first conductive layer and the conductive spacers. A second conductive layer is formed on the second dielectric layer. A third conducive layer is formed on the second conductive layer, passes though a portion of the second conductive layer and the second dielectric layer, and contacts the first conductive layer. The third conductive layer electrically connects the first and second conductive layers.
摘要翻译： NAND存储器阵列的选择栅极具有形成在半导体衬底上的第一电介质层。在第一电介质层上形成第一导电层。导电间隔物形成在第一导电层的侧壁上，并且位于第一导电层的上表面和第一介电层之间。第二电介质层覆盖在第一导电层和导电间隔物之间。在第二电介质层上形成第二导电层。第三导电层形成在第二导电层上，穿过第二导电层和第二介电层的一部分，并与第一导电层接触。第三导电层电连接第一和第二导电层。

16. 发明授权

US07332408B2 Isolation trenches for memory devices 有权
标题翻译：存储器件的隔离沟槽
公开(公告)号：US07332408B2
公开(公告)日：2008-02-19
申请号：US10878805
申请日：2004-06-28
申请人： Michael Violette
发明人： Michael Violette
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L27/11517
摘要： Methods and apparatus are provided. A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.
摘要翻译：提供了方法和装置。第一电介质塞形成在延伸到存储器件的衬底中的沟槽的一部分中，使得第一电介质插塞的上表面凹陷在衬底的上表面下方。第一电介质插塞具有形成在第一电介质材料层上的第一电介质材料层和第二电介质材料层。第三绝缘材料的第二电介质塞形成在第一电介质塞的上表面上。

17. 发明授权

US06245604B1 Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits 失效
标题翻译：用于制造集成电路的双极CMOS（BiCMOS）工艺
公开(公告)号：US06245604B1
公开(公告)日：2001-06-12
申请号：US08585453
申请日：1996-01-16
申请人： Michael Violette , Martin Ceredig Roberts
发明人： Michael Violette , Martin Ceredig Roberts
IPC分类号： H01L218249
CPC分类号： H01L21/8249
摘要： A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO2/Si3N4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.
摘要翻译：使用最少数量的晶圆处理步骤制造BiCMOS集成电路，并提供IC电路设计器五（5）种不同的晶体管类型。这些类型包括P沟道和N沟道MOS晶体管以及三个不同的双极晶体管，其发射极都由不同的工艺形成，并且都以不同的电流增益和不同的击穿电压为特征。在IC制造工艺中使用差示二氧化硅/氮化硅掩蔽技术，其中使用单个掩模组在硅衬底中形成P型掩埋层（PBL）和N型掩埋层（NBL），并且其中P 类型的阱和N型阱在外延层上形成在这些掩埋层上方，也使用单个SiO 2 / Si 3 N 4差分掩模集合。两个双极晶体管发射极通过从第一和第二层多晶硅的扩散形成，而第三双极晶体管的发射极通过离子注入掺杂形成。

18. 发明授权

US6043541A Bipolar-CMOS (BiCMOS) process for fabricating integrated circuits 有权
公开(公告)号：US6043541A
公开(公告)日：2000-03-28
申请号：US140497
申请日：1998-08-27
申请人： Michael Violette , Martin Ceredig Roberts
发明人： Michael Violette , Martin Ceredig Roberts
IPC分类号： H01L21/8249 , H01L29/76
CPC分类号： H01L21/8249
摘要： A BiCMOS integrated circuit is fabricated using a minimum number of wafer processing steps and yet offers the IC circuit designer five (5) different transistor types. These types include P-channel and N-channel MOS transistors and three different bipolar transistors whose emitters are all formed by a different process and all are characterized by different current gains and different breakdown voltages. A differential silicon dioxide/silicon nitride masking technique is used in the IC fabrication process wherein both P-type buried layers (PBL) and N-type buried layers (NBL) are formed in a silicon substrate using a single mask set and further wherein P-type wells and N-type wells are formed above these buried layers in an epitaxial layer, also using a single SiO.sub.2 /Si.sub.3 N.sub.4 differential mask set. Two of the bipolar transistor emitters are formed by out diffusion from first and second levels of polysilicon, whereas the emitter of the third bipolar transistor is formed by ion implantation doping.

19. 发明申请

US20110012186A1 ISOLATION TRENCHES FOR MEMORY DEVICES 有权
标题翻译：用于存储器件的隔离开关
公开(公告)号：US20110012186A1
公开(公告)日：2011-01-20
申请号：US12891248
申请日：2010-09-27
申请人： Michael Violette
发明人： Michael Violette
IPC分类号： H01L29/788 , H01L21/762 , H01L29/06
CPC分类号： H01L21/76232 , H01L27/11517
摘要： A first dielectric plug is formed in a portion of a trench that extends into a substrate of a memory device so that an upper surface of the first dielectric plug is recessed below an upper surface of the substrate. The first dielectric plug has a layer of a first dielectric material and a layer of a second dielectric material formed on the layer of the first dielectric material. A second dielectric plug of a third dielectric material is formed on the upper surface of the first dielectric plug.
摘要翻译：第一电介质塞形成在延伸到存储器件的衬底中的沟槽的一部分中，使得第一电介质插塞的上表面凹陷在衬底的上表面下方。第一电介质插塞具有形成在第一电介质材料层上的第一电介质材料层和第二电介质材料层。第三绝缘材料的第二电介质塞形成在第一电介质塞的上表面上。

20. 发明授权

US07439157B2 Isolation trenches for memory devices 有权
标题翻译：存储器件的隔离沟槽
公开(公告)号：US07439157B2
公开(公告)日：2008-10-21
申请号：US11129884
申请日：2005-05-16
申请人： Zailong Bian , John Smythe , Janos Fucsko , Michael Violette
发明人： Zailong Bian , John Smythe , Janos Fucsko , Michael Violette
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L27/11517
摘要： A method includes removing a portion of a substrate to define an isolation trench; forming a first dielectric layer on exposed surfaces of the substrate in the trench; forming a second dielectric layer on at least the first dielectric layer, the second dielectric layer containing a different dielectric material than the first dielectric layer; depositing a third dielectric layer to fill the trench; removing an upper portion of the third dielectric layer from the trench and leaving a lower portion covering a portion of the second dielectric layer; oxidizing the lower portion of the third dielectric layer after removing the upper portion; removing an exposed portion of the second dielectric layer from the trench, thereby exposing a portion of the first dielectric layer; and forming a fourth dielectric layer in the trench covering the exposed portion of the first dielectric layer.
摘要翻译：一种方法包括去除衬底的一部分以限定隔离沟槽; 在所述沟槽中的所述衬底的暴露表面上形成第一电介质层; 在至少所述第一介电层上形成第二电介质层，所述第二电介质层含有与所述第一电介质层不同的电介质材料; 沉积第三介电层以填充沟槽; 从沟槽移除第三电介质层的上部并留下覆盖第二介电层的一部分的下部; 在除去上部之后氧化第三电介质层的下部; 从所述沟槽去除所述第二电介质层的暴露部分，从而暴露所述第一介电层的一部分; 以及在所述沟槽中形成覆盖所述第一介电层的暴露部分的第四电介质层。

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