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11. 发明授权

US08041518B2 Determining die test protocols based on process health 有权
标题翻译：基于过程健康确定模具测试方案
公开(公告)号：US08041518B2
公开(公告)日：2011-10-18
申请号：US11745688
申请日：2007-05-08
申请人： Michael G. McIntyre , Kevin R. Lensing
发明人： Michael G. McIntyre , Kevin R. Lensing
IPC分类号： G01R15/00
CPC分类号： G01R31/2894
摘要： A method includes receiving a first set of parameters associated with a subset of a plurality of die on a wafer. A die health metric is determined for at least a portion of the plurality of die based on the first set of parameters. The die health metric includes at least one process component associated with the fabrication of the die and at least one performance component associated with an electrical performance characteristic of the die. At least one of the die is tested. A protocol of the testing is determined based on the associated die health metric.
摘要翻译：一种方法包括接收与晶片上的多个管芯的子集相关联的第一组参数。基于第一组参数为多个管芯的至少一部分确定管芯健康度量。模具健康度量包括与模具的制造相关联的至少一个工艺部件和与模具的电性能特性相关联的至少一个性能部件。至少有一个模具被测试。测试的协议基于相关的模具健康度量来确定。

12. 发明申请

US20110137597A1 METHOD AND APPARATUS FOR ANALYSIS OF CONTINOUS DATA USING BINARY PARSING 失效
标题翻译：使用二进制分析进行连续数据分析的方法和装置
公开(公告)号：US20110137597A1
公开(公告)日：2011-06-09
申请号：US13016528
申请日：2011-01-28
申请人： Michael G. McIntyre , Michael A. Retersdorf
发明人： Michael G. McIntyre , Michael A. Retersdorf
IPC分类号： G06F19/00 , G01N37/00
CPC分类号： H01L22/20 , H01L22/14
摘要： A method, apparatus, and a system for generating a binary mapping of wafer regions using measured value. A first measured value relating to processing a first workpiece is acquired. A second measured value relating to a second workpiece is acquired. At least a first region common to the first and second workpieces is defined. A determination is made as to whether the results associated with the first or second measured value is above a predetermined threshold. A first binary value is assigned to the first region based upon a determination that the results associated the first or second measured value data is above the threshold.
摘要翻译：一种用于使用测量值产生晶片区域的二进制映射的方法，装置和系统。获取与处理第一工件有关的第一测量值。获得与第二工件相关的第二测量值。至少限定了第一和第二工件共同的第一区域。确定与第一或第二测量值相关联的结果是否高于预定阈值。基于与第一或第二测量值数据相关联的结果高于阈值的确定，将第一二进制值分配给第一区域。

13. 发明授权

US06297644B1 Multipurpose defect test structure with switchable voltage contrast capability and method of use 有权
标题翻译：具有可切换电压对比度的多用途缺陷测试结构和使用方法
公开(公告)号：US06297644B1
公开(公告)日：2001-10-02
申请号：US09262240
申请日：1999-03-04
申请人： Richard W. Jarvis , Iraj Emami , John L. Nistler , Michael G. McIntyre
发明人： Richard W. Jarvis , Iraj Emami , John L. Nistler , Michael G. McIntyre
IPC分类号： H01H3102
CPC分类号： G01R31/306 , G01R31/309
摘要： A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than the floating conductive lines when the test structure is inspected. If a short occurs between the conductive lines, due to an extra material defect, the portion of the floating line in the vicinity of the defect will also appear darkened. If an open appears along a grounded line, the non-grounded portion of the grounded line will be glowing. The grounded conductive lines are preferably grounded through a depletion-mode transistor. By applying a voltage to the transistor, the grounded line may be disconnected from ground, allowing electrical testing of the test structure. The electrical testing may be used to validate the voltage contrast methodology, as well as determine the approximate size of defects formed on the test structure.
摘要翻译：包括交替接地和浮动导线的测试结构可用于测试集成电路形貌上的导电特征的形成。在从电子源照射导线时，当检查结构时，接地的导线将比浮动导线显得更暗。如果在导线之间发生短路，由于额外的材料缺陷，在缺陷附近的浮线部分也将变暗。如果沿接地线路出现开路，接地线路的非接地部分将发光。接地的导线优选通过耗尽型晶体管接地。通过向晶体管施加电压，接地线可能与地断开，从而允许测试结构的电气测试。电气测试可用于验证电压对比度方法，以及确定在测试结构上形成的缺陷的大致尺寸。

14. 发明授权

US08239151B2 Method and apparatus for analysis of continuous data using binary parsing 失效
标题翻译：使用二进制解析分析连续数据的方法和装置
公开(公告)号：US08239151B2
公开(公告)日：2012-08-07
申请号：US13016528
申请日：2011-01-28
申请人： Michael G. McIntyre , Michael A. Retersdorf
发明人： Michael G. McIntyre , Michael A. Retersdorf
IPC分类号： G01N37/00
CPC分类号： H01L22/20 , H01L22/14
摘要： A method, apparatus, and a system for generating a binary mapping of wafer regions using measured value. A first measured value relating to processing a first workpiece is acquired. A second measured value relating to a second workpiece is acquired. At least a first region common to the first and second workpieces is defined. A determination is made as to whether the results associated with the first or second measured value is above a predetermined threshold. A first binary value is assigned to the first region based upon a determination that the results associated the first or second measured value data is above the threshold.
摘要翻译：一种用于使用测量值产生晶片区域的二进制映射的方法，装置和系统。获取与处理第一工件有关的第一测量值。获得与第二工件相关的第二测量值。至少限定了第一和第二工件共同的第一区域。确定与第一或第二测量值相关联的结果是否高于预定阈值。基于与第一或第二测量值数据相关联的结果高于阈值的确定，将第一二进制值分配给第一区域。

15. 发明授权

US07710137B2 Method and apparatus for relative testing of integrated circuit devices 有权
标题翻译：集成电路器件的相对测试方法和装置
公开(公告)号：US07710137B2
公开(公告)日：2010-05-04
申请号：US11849702
申请日：2007-09-04
申请人： Michael G. McIntyre
发明人： Michael G. McIntyre
IPC分类号： G01R31/02
CPC分类号： G01R31/31718
摘要： A method includes loading a plurality of integrated circuit devices into a tester. At least one parameter is determined for each of the integrated circuit devices using the tester. At least one relative acceptance criterion associated with the parameter is determined based on the determined parameters for the plurality of integrated circuit devices. A pass/fail status of each of the integrated circuit devices is determined using the relative acceptance criterion.
摘要翻译：一种方法包括将多个集成电路装置加载到测试器中。使用测试仪为每个集成电路器件确定至少一个参数。基于所确定的多个集成电路装置的参数来确定与参数相关联的至少一个相对接受标准。使用相对接受标准来确定每个集成电路器件的通过/失败状态。

16. 发明授权

US07236848B2 Data representation relating to a non-sampled workpiece 有权
标题翻译：与未采样的工件有关的数据表示
公开(公告)号：US07236848B2
公开(公告)日：2007-06-26
申请号：US11224388
申请日：2005-09-12
申请人： Steven P. Reeves , Michael G. McIntyre
发明人： Steven P. Reeves , Michael G. McIntyre
IPC分类号： G06F19/00
CPC分类号： G05B19/41865 , G05B19/4183 , G05B2219/32075 , G05B2219/32194 , G05B2219/37222 , G05B2219/45031 , Y02P90/10 , Y02P90/20 , Y02P90/22
摘要： A method, apparatus, and a system for providing data representation associated with non-sampled workpieces. Measured metrology data relating to a first workpiece is received. Metrology data corresponding to a second workpiece is approximated based upon the metrology data relating to the first workpiece to provide a projected metrology data relating to the second workpiece.
摘要翻译：一种用于提供与未采样工件相关联的数据表示的方法，装置和系统。接收与第一工件相关的测量的测量数据。基于与第一工件相关的计量数据来近似对应于第二工件的计量数据，以提供与第二工件相关的投影度量数据。

17. 发明授权

US07195931B2 Split manufacturing method for advanced semiconductor circuits 失效
标题翻译：先进的半导体电路分裂制造方法
公开(公告)号：US07195931B2
公开(公告)日：2007-03-27
申请号：US10305670
申请日：2002-11-27
申请人： Richard Wayne Jarvis , Michael G. McIntyre
发明人： Richard Wayne Jarvis , Michael G. McIntyre
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L22/20 , H01L23/544 , H01L24/48 , H01L2223/5442 , H01L2223/54473 , H01L2223/5448 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01322 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： A front-end-of-line piece of a semiconductor die is manufactured in a first manufacturing line. A back-end-of-line piece of a semiconductor die is manufactured using a second manufacturing line, which will typically be different than the first manufacturing line. The front-end-of-line piece and the back-end-of-line piece are combined during a joining process to form a semiconductor die. The semiconductor die is subsequently tested to determine if the semiconductor die is a functional semiconductor die.
摘要翻译：在第一生产线中制造半导体管芯的前端片。使用通常不同于第一生产线的第二生产线来制造半导体管芯的后端管件。在接合过程期间组合前端片和后端片，以形成半导体管芯。随后测试半导体管芯以确定半导体管芯是否是功能半导体管芯。

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