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11. 发明授权

US06768185B2 Formation of antifuse structure in a three dimensional memory 有权
标题翻译：在三维记忆体中形成反熔丝结构
公开(公告)号：US06768185B2
公开(公告)日：2004-07-27
申请号：US10114451
申请日：2002-04-01
申请人： James M. Cleeves , Michael A. Vyvoda , N. Johan Knall
发明人： James M. Cleeves , Michael A. Vyvoda , N. Johan Knall
IPC分类号： H01L2900
CPC分类号： H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： The present invention is directed to novel antifuse arrays and their methods of fabrication. According to an embodiment of the present invention an array comprises a plurality of first spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric extends above the top surface of the semiconductor material. An antifuse material is formed on the top of the semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor material is formed on the antifuse material. In the second embodiment of the present invention the array comprises a first plurality of spaced apart rail-stacks having a top semiconductor material. A fill dielectric is located between the first plurality of spaced apart rail-stacks wherein the fill dielectric is recessed below the top surface of the semiconductor material. An antifuse material is formed on the top semiconductor material of the first plurality of spaced apart rail-stacks. A second plurality of spaced apart rail-stacks having a lower semiconductor film is formed on the antifuse material.
摘要翻译：本发明涉及新颖的反熔丝阵列及其制造方法。根据本发明的实施例，阵列包括具有顶部半导体材料的多个第一间隔开的轨道堆叠。填充电介质位于第一多个间隔开的轨道堆叠之间，其中填充电介质延伸到半导体材料的顶表面之上。在第一多个间隔开的轨道堆叠的半导体材料的顶部上形成反熔丝材料。在反熔丝材料上形成具有下半导体材料的第二多个间隔开的轨道堆叠。在本发明的第二实施例中，阵列包括具有顶部半导体材料的第一多个间隔开的轨道堆叠。填充电介质位于第一多个间隔开的轨道堆叠之间，其中填充电介质凹陷在半导体材料的顶表面下方。在第一多个间隔开的轨道堆叠的顶部半导体材料上形成反熔丝材料。在反熔丝材料上形成具有下半导体膜的第二多个间隔开的轨道堆叠。

12. 发明授权

US06704235B2 Anti-fuse memory cell with asymmetric breakdown voltage 有权
标题翻译：具有不对称击穿电压的反熔丝存储单元
公开(公告)号：US06704235B2
公开(公告)日：2004-03-09
申请号：US10027466
申请日：2001-12-20
申请人： N. Johan Knall , James M. Cleeves , Igor G. Kouznetsov , Michael A. Vyvoda
发明人： N. Johan Knall , James M. Cleeves , Igor G. Kouznetsov , Michael A. Vyvoda
IPC分类号： H01L2904
CPC分类号： H01L27/101 , G11C17/16 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A memory cell for a two- or a three-dimensional memory array includes first and second conductors and set of layers situated between the conductors. This set of layers includes a dielectric rupture anti-fuse layer having a thickness less than 35 Å and a leakage current density (in the unruptured state) greater than 1 mA/cm2 at 2 V. This low thickness and high current leakage density provide a memory cell with an asymmetric dielectric layer breakdown voltage characteristic. The antifuse layer is formed of an antifuse material characterized by a thickness Tminlife at which the antifuse material is ruptured by a minimum number of write pulses having a polarity that reverse biases diode components included in the memory cell. The average thickness T of the antifuse layer is less than the thickness Tminlife.
摘要翻译：用于二维或三维存储器阵列的存储单元包括位于导体之间的第一和第二导体和一组层。这组层包括厚度小于35A的电介质破裂抗熔丝层和在2V时大于1mA / cm 2的漏电流密度（在未破裂状态下）。这种低厚度和高电流泄漏密度提供具有不对称介电层击穿电压特性的存储单元。反熔丝层由反熔丝材料形成，其特征在于厚度Tminmin，其中反熔丝材料被最小数量的具有反向偏置存储单元中包含的二极管组件的极性的写入脉冲破裂。反熔丝层的平均厚度T小于厚度Tminlife。

13. 发明授权

US06954394B2 Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions 有权
标题翻译：用于选择一组存储单元层相关或依赖于温度的操作条件的集成电路和方法
公开(公告)号：US06954394B2
公开(公告)日：2005-10-11
申请号：US10307270
申请日：2002-11-27
申请人： N. Johan Knall , Roy E. Scheuerlein , James M. Cleeves , Bendik Kleveland , Mark G. Johnson
发明人： N. Johan Knall , Roy E. Scheuerlein , James M. Cleeves , Bendik Kleveland , Mark G. Johnson
IPC分类号： G11C7/10 , G11C7/18 , G11C7/22 , G11C29/50 , G11C7/04 , G11C5/06
CPC分类号： G11C29/028 , G11C7/04 , G11C7/1045 , G11C7/18 , G11C7/22 , G11C29/50 , G11C29/50012 , G11C2029/5002 , G11C2207/2281 , G11C2207/229
摘要： The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译：本文所述的优选实施例涉及用于选择一组存储单元层相关或依赖于温度的操作条件的集成电路和方法。在一个优选实施例中，提供一种存储器阵列，其包括布置在单个集成电路中彼此垂直堆叠的L层的多个存储单元。选择存储器阵列中的存储器单元层，并且基于所选择的存储器来选择N组存储器单元层相关写入条件和/或K组存储器单元层相关读取条件中的一个细胞层。在另一个优选实施例中，测量集成电路的温度，并且基于测量的温度选择一组写入条件和/或一组读取条件。提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

14. 发明授权

US6019658A Fabrication of gated electron-emitting device utilizing distributed particles to define gate openings, typically in combination with spacer material to control spacing between gate layer and electron-emissive elements 有权
标题翻译：使用分布式颗粒来限定栅极开口的门控电子发射器件的制造，通常与间隔物材料组合以控制栅极层和电子发射元件之间的间隔
公开(公告)号：US6019658A
公开(公告)日：2000-02-01
申请号：US151924
申请日：1998-09-11
申请人： Paul N. Ludwig , Duane A. Haven , John M. Macaulay , Christopher J. Spindt , James M. Cleeves , N. Johan Knall
发明人： Paul N. Ludwig , Duane A. Haven , John M. Macaulay , Christopher J. Spindt , James M. Cleeves , N. Johan Knall
IPC分类号： H01J9/02
CPC分类号： H01J9/025 , H01J2329/00
摘要： A gated electron-emitter having a lower non-insulating emitter region (42), an overlying insulating layer (44), and a gate layer (48A, 60A, 60B, 120A, or 180A/184) is fabricated by a process in which particles (46) are distributed over the insulating layer, the gate layer, a primary layer (50A, 62A, or 72) provided over the gate layer, a further layer (74) provided over the primary layer, or a pattern-transfer layer (182). The particles are utilized in defining gate openings (54, 66, 80, 122, or 186/188) through the gate layer. Spacer material is provided along the edges of the gate openings to form spacers (102A, 110A, 124A, 140, or 150B). Dielectric openings (80, 114, 128, 144, or 154) are formed through the insulating layer. The dielectric openings can be created before or after creating the spacers. In either case, emitter material in introduced into either the full dielectric openings, or into the portions of the dielectric openings not covered with spacer material, to form electron-emissive elements (106B, 116B, 130A, 146A, or 156B) typically filamentary in shape.
摘要翻译：具有较低非绝缘发射极区域（42），上覆绝缘层（44）和栅极层（48A，60A，60B，120A或180A / 184）的门控电子发射器通过以下工艺制造，其中颗粒（46）分布在绝缘层上，栅极层，设置在栅极层上的主层（50A，62A或72），设置在主层上的另一层（74）或图案转移层（182）。这些颗粒用于通过栅极层限定栅极开口（54,66,80,122或186/188）。间隔材料沿栅极开口的边缘设置以形成间隔物（102A，110A，124A，140或150B）。通过绝缘层形成电介质开口（80,114,128,144或154）。可以在产生间隔物之前或之后产生电介质开口。在任一种情况下，发射体材料被引入到完整电介质开口中，或者被引入未被间隔物材料覆盖的电介质开口部分，以形成电子发射元件（106B，116B，130A，146A或156B），通常为形状。

15. 发明授权

US5865659A Fabrication of gated electron-emitting device utilizing distributed particles to define gate openings and utilizing spacer material to control spacing between gate layer and electron-emissive elements 失效
标题翻译：使用分布式颗粒来限定栅极开口并利用间隔物材料来控制栅极层和电子发射元件之间的间隔的门控电子发射器件的制造
公开(公告)号：US5865659A
公开(公告)日：1999-02-02
申请号：US660538
申请日：1996-06-07
申请人： Paul N. Ludwig , Duane A. Haven , John M. Macaulay , Christopher J. Spindt , James M. Cleeves , N. Johan Knall
发明人： Paul N. Ludwig , Duane A. Haven , John M. Macaulay , Christopher J. Spindt , James M. Cleeves , N. Johan Knall
IPC分类号： H01J9/02 , H01J1/30
CPC分类号： H01J9/025 , H01J2329/00
摘要： A gated electron-emitter having a lower non-insulating emitter region (42), an overlying insulating layer (44), and a gate layer (48A, 60A, 60B, 120A, or 180A/184) is fabricated by a process in which particles (46) are distributed over the insulating layer, the gate layer, a primary layer (50A, 62A, or 72) provided over the gate layer, a further layer (74) provided over the primary layer, or a pattern-transfer layer (182). The particles are utilized in defining gate openings (54, 66, 80, 122, or 186/188) through the gate layer. Spacer material is provided along the edges of the gate openings to form spacers (110A, 124A, 140, or 150B) but leave corresponding apertures (112A, 126A, 142, or 152) through the spacer material. The insulating layer is etched through the apertures to form dielectric openings (114, 128, 144, or 154) through the insulating layer. Emitter material is introduced into the dielectric openings to form electron-emissive elements (116B, 130A, 146A, or 156B) typically filamentary in shape.
摘要翻译：具有较低非绝缘发射极区域（42），上覆绝缘层（44）和栅极层（48A，60A，60B，120A或180A / 184）的门控电子发射器通过以下工艺制造，其中颗粒（46）分布在绝缘层上，栅极层，设置在栅极层上的主层（50A，62A或72），设置在主层上的另一层（74）或图案转移层（182）。这些颗粒用于通过栅极层限定栅极开口（54,66,80,122或186/188）。隔板材料沿栅极开口的边缘设置以形成间隔物（110A，124A，140或150B），但通过间隔物料留下相应的孔（112A，126A，142或152）。通过孔蚀刻绝缘层，以形成通过绝缘层的电介质开口（114,128,144或154）。将发射体材料引入电介质开口以形成通常为丝状形状的电子发射元件（116B，130A，146A或156B）。

16. 发明授权

US06982476B2 Integrated circuit feature layout for improved chemical mechanical polishing 有权
标题翻译：集成电路特性布局，用于改进化学机械抛光
公开(公告)号：US06982476B2
公开(公告)日：2006-01-03
申请号：US10800078
申请日：2004-03-12
申请人： James M. Cleeves , Michael A. Vyvoda
发明人： James M. Cleeves , Michael A. Vyvoda
IPC分类号： H01L23/544 , H01L29/73
CPC分类号： C04B35/44 , C04B35/63 , C04B35/634 , C04B35/63404 , C04B41/5032 , C04B41/52 , C04B41/87 , C04B41/89 , C04B2235/3217 , C04B2235/3224 , C04B2235/3225 , C04B2235/3227 , C04B2235/3244 , C04B2235/72 , C04B2235/96 , H01L21/3212 , H01L21/76819 , H01L21/7684 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.
摘要翻译：本发明是集成电路的电平。集成电路的电平具有具有第一密度的多个特征的第一区域，并且集成电路的电平具有与第一区域相邻的第二区域，其中第二区域具有多个虚拟特征，密度基本上类似于第一密度。

17. 发明授权

US06486066B2 Method of generating integrated circuit feature layout for improved chemical mechanical polishing 有权
标题翻译：生成集成电路特征布局以改进化学机械抛光的方法
公开(公告)号：US06486066B2
公开(公告)日：2002-11-26
申请号：US09775761
申请日：2001-02-02
申请人： James M. Cleeves , Michael A. Vyvoda
发明人： James M. Cleeves , Michael A. Vyvoda
IPC分类号： H01L2182
CPC分类号： C04B35/44 , C04B35/63 , C04B35/634 , C04B35/63404 , C04B41/5032 , C04B41/52 , C04B41/87 , C04B41/89 , C04B2235/3217 , C04B2235/3224 , C04B2235/3225 , C04B2235/3227 , C04B2235/3244 , C04B2235/72 , C04B2235/96 , H01L21/3212 , H01L21/76819 , H01L21/7684 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.
摘要翻译：本发明是集成电路的电平。集成电路的电平具有具有第一密度的多个特征的第一区域，并且集成电路的电平具有与第一区域相邻的第二区域，其中第二区域具有多个虚拟特征，密度基本上类似于第一密度。

18. 发明授权

US06649451B1 Structure and method for wafer comprising dielectric and semiconductor 失效
标题翻译：包括电介质和半导体的晶片的结构和方法
公开(公告)号：US06649451B1
公开(公告)日：2003-11-18
申请号：US09776000
申请日：2001-02-02
申请人： Michael A. Vyvoda , James M. Cleeves , Calvin K. Li , Samuel V. Dunton
发明人： Michael A. Vyvoda , James M. Cleeves , Calvin K. Li , Samuel V. Dunton
IPC分类号： H01L2182
CPC分类号： H01L21/76224 , H01L21/76819 , H01L23/5254 , H01L27/10 , H01L2924/0002 , H01L2924/00
摘要： Wafers of the present invention comprise a semiconductor layer and a dielectric layer. The semiconductor layer is patterned to form semiconductor regions, and the dielectric layer is deposited on top of the semiconductor layer. Chemical mechanical planarization (CMP) is performed to remove a portion of the dielectric layer, exposing the upper surfaces of the semiconductor regions. The amount of CMP necessary to expose all of the semiconductor regions on the wafer is reduced, because the dielectric is targeted to deposit up to the upper edge of the semiconductor regions in the spaces in between the semiconductor regions. This technique reduces non-uniformities in the thickness of the dielectric and semiconductor layers across the wafer. The thickness of the dielectric or semiconductor layer deposited on polish monitor pads located at the edges of each die may be monitored to determine when enough CMP has been performed to expose each of the semiconductor regions.
摘要翻译：本发明的晶片包括半导体层和电介质层。图案化半导体层以形成半导体区域，并且电介质层沉积在半导体层的顶部上。执行化学机械平面化（CMP）以去除电介质层的一部分，暴露半导体区域的上表面。由于电介质被靶向沉积到半导体区域之间的空间中的半导体区域的上边缘，因此减小了使晶片上的所有半导体区域露出所需的CMP量。该技术降低了跨晶片的电介质层和半导体层的厚度的不均匀性。可以监测沉积在位于每个管芯边缘的抛光监测器焊盘上的电介质层或半导体层的厚度，以确定何时已经执行了足够的CMP来暴露每个半导体区域。

19. 发明授权

US06730931B2 Integrated circuit feature layout for improved chemical mechanical polishing 有权
标题翻译：集成电路特性布局，用于改进化学机械抛光
公开(公告)号：US06730931B2
公开(公告)日：2004-05-04
申请号：US09935862
申请日：2001-08-22
申请人： James M. Cleeves , Michael A. Vyvoda
发明人： James M. Cleeves , Michael A. Vyvoda
IPC分类号： H01L2358
CPC分类号： C04B35/44 , C04B35/63 , C04B35/634 , C04B35/63404 , C04B41/5032 , C04B41/52 , C04B41/87 , C04B41/89 , C04B2235/3217 , C04B2235/3224 , C04B2235/3225 , C04B2235/3227 , C04B2235/3244 , C04B2235/72 , C04B2235/96 , H01L21/3212 , H01L21/76819 , H01L21/7684 , H01L23/528 , H01L2924/0002 , Y10S438/926 , H01L2924/00
摘要： The present invention is a level of an integrated circuit. The level of integrated circuit has a first area having a plurality of features having a first density and the level of the integrated circuit has a second area adjacent to the first area wherein the second area has a plurality of dummy features having a density substantially similar to the first density.
摘要翻译：本发明是集成电路的电平。集成电路的电平具有具有第一密度的多个特征的第一区域，并且集成电路的电平具有与第一区域相邻的第二区域，其中第二区域具有多个虚拟特征，密度基本上类似于第一密度。

20. 发明授权

US09650951B2 Single piston sleeve valve with optional variable compression ratio capability 有权
公开(公告)号：US09650951B2
公开(公告)日：2017-05-16
申请号：US13270200
申请日：2011-10-10
申请人： James M. Cleeves , Simon David Jackson , Michael Hawkes , Michael A. Willcox
发明人： James M. Cleeves , Simon David Jackson , Michael Hawkes , Michael A. Willcox
IPC分类号： F02B75/04 , F02D15/04 , F02D15/00 , F01L5/06 , F01L7/04
CPC分类号： F02B75/042 , F01L5/06 , F01L7/04 , F02B75/041 , F02D15/04
摘要： An internal combustion engine can include a piston moving in a cylinder and a junk head disposed opposite the piston head in the cylinder. The junk head can optionally be moveable between a higher compression ratio position closer to a top dead center of the piston and a lower compression ratio position further from the top dead center position of the piston. At least one intake port can deliver a fluid comprising inlet air to a combustion chamber within the cylinder. Combustion gases can be directed out of the combustion volume through at least one exhaust port. One or both of the intake port and the exhaust port can be opened and closed by operation of a sleeve valve that at least partially encircles the piston. Related articles, systems, and methods are described.

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