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    • 20. 发明申请
    • INFORMATION PROCESSING DEVICE AND INFORMATION PROCESSING METHOD
    • 信息处理设备和信息处理方法
    • US20070300126A1
    • 2007-12-27
    • US11677216
    • 2007-02-21
    • Yoshihiro NakaoIsao Kimura
    • Yoshihiro NakaoIsao Kimura
    • H03M13/09
    • H03M13/05H04L1/0041H04L1/0057H04L2001/0097
    • An information processing device implements error control including at least one of error detection and error correction. The device comprises an information bit sequence acquiring unit and an encoder. The information bit sequence acquiring unit acquires an information bit sequence. The encoder generates a redundant bit sequence enabling execution of error control of the entire information bit sequence, the redundant bit sequence being generated through encoding by a predetermined code based on the information bit sequence and generates a codeword that includes the information bit sequence and the redundant bit sequence. The encoder generates the redundant bit sequence in such a way that one or more bits contained in the redundant bit sequence each functions as a parity bit for one of a plurality of divided information bit sequences produced by dividing the information bit sequence.
    • 信息处理设备实现包括错误检测和纠错中的至少一个的错误控制。 该装置包括信息比特序列获取单元和编码器。 信息比特序列获取单元获取信息比特序列。 编码器产生冗余比特序列,使得能够执行整个信息比特序列的错误控制,该冗余比特序列是通过基于信息比特序列的预定码进行编码而产生的,并产生包括信息比特序列和冗余的码字 位序列。 编码器以这样的方式生成冗余比特序列,使得包含在冗余比特序列中的一个或多个比特各自用作通过划分信息比特序列而产生的多个划分的信息比特序列之一的奇偶校验位。