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11. 发明申请

US20050066209A1 Portable electronic device having high and low power processors operable in a low power mode 审中-公开
标题翻译：具有可在低功率模式下操作的高功率和低功率处理器的便携式电子设备
公开(公告)号：US20050066209A1
公开(公告)日：2005-03-24
申请号：US10871871
申请日：2004-06-17
申请人： Martin Kee , Chao-Chi Chen , Rod Fleck , Craig O'Connell , Stephen Perrin , Michael Clarke
发明人： Martin Kee , Chao-Chi Chen , Rod Fleck , Craig O'Connell , Stephen Perrin , Michael Clarke
IPC分类号： G06F20060101 , G06F1/26
CPC分类号： G06F1/3293 , G06F1/1616 , G06F1/165 , G06F1/1656 , G06F1/1671 , G06F1/1684 , G06F1/1698 , G06F1/3287 , Y02D10/122 , Y02D10/171 , Y02D50/20 , Y02D70/10 , Y02D70/14
摘要： A computer system has a main display attached to a computer chassis. The computer chassis includes a high power, high performance main processor running applications on a first operating system platform. The auxiliary display module has a low power, low performance auxiliary processor, a small touch-screen display and a keypad. The main processor interfaces with a keyboard on the upper surface of the chassis and a main display. In a high power mode, there is no display and keypad input in the auxiliary display module. In a power sleep mode, power is removed from the first processor, the main display and many of the components in the computer chassis. However, key functions, such as email, a contact list, and an appointment calendar can be accessed using the auxiliary display module. In a low power mode, the main display shuts off and many of the components in the computer chassis are powered down. However, key functions, such as email, a contact list, an appointment calendar, and a media player, can be accessed using the auxiliary display module.
摘要翻译：计算机系统具有连接到计算机机箱的主显示器。计算机机箱包括在第一操作系统平台上运行应用程序的大功率，高性能主处理器。辅助显示模块具有低功率，低性能的辅助处理器，小型触摸屏显示器和小键盘。主处理器与机箱上表面的键盘和主显示器相连。在高功率模式下，辅助显示模块中没有显示屏和键盘输入。在电源休眠模式下，电源从第一个处理器，主显示器和计算机机箱中的许多组件中删除。然而，可以使用辅助显示模块访问诸如电子邮件，联系人列表和约会日历之类的关键功能。在低功耗模式下，主显示屏关闭，计算机机箱中的许多组件已断电。然而，可以使用辅助显示模块访问诸如电子邮件，联系人列表，约会日历和媒体播放器的关键功能。

12. 发明授权

US07844055B2 Detecting and transporting dynamic presence information over a wireless and wireline communications network 有权
标题翻译：通过无线和有线通信网络检测和传输动态存在信息
公开(公告)号：US07844055B2
公开(公告)日：2010-11-30
申请号：US10180636
申请日：2002-06-25
申请人： Atanu Mukherjee , Francois Frederic Ozog , Chao-Chi Chen
发明人： Atanu Mukherjee , Francois Frederic Ozog , Chao-Chi Chen
IPC分类号： G06F15/16 , H04W4/00 , H04W36/00
CPC分类号： H04L65/103 , H04L29/06 , H04L29/06027 , H04L29/12207 , H04L51/00 , H04L51/04 , H04L51/38 , H04L61/20 , H04L65/1006 , H04L65/104 , H04L65/1043 , H04L67/04 , H04L67/18 , H04L67/24 , H04L67/26 , H04L67/2823 , H04L67/2828 , H04L67/2842 , H04L67/303 , H04L69/08 , H04L69/24 , H04L69/329 , H04W4/02 , H04W4/06 , H04W8/10 , H04W8/183 , H04W8/205 , H04W8/22 , H04W60/04
摘要： A method for detecting and transporting dynamic presence information over a wireless and wireline communications network comprises determining client device capabilities relating to user presence information that may be obtained from the client device and determining a presence configuration of the client device. The presence configuration defines information to be provided to a presence agent. The presence configuration also defines one or more action to be performed upon notification of an event occurrence. The method also includes collecting dynamic presence information based at least in part on the client device capabilities and the presence configuration.
摘要翻译：一种用于通过无线和有线通信网络检测和传送动态存在信息的方法包括确定与可从客户端设备获得的用户存在信息相关的客户端设备能力并确定客户端设备的存在配置。存在配置定义要提供给存在代理的信息。存在配置还定义了在事件发生通知时要执行的一个或多个动作。该方法还包括至少部分地基于客户端设备能力和存在配置来收集动态存在信息。

13. 发明申请

US20160020825A1 INPUT/OUTPUT SIGNAL PROCESSING CIRCUIT AND INPUT/OUTPUT SIGNAL PROCESSING METHOD 有权
公开(公告)号：US20160020825A1
公开(公告)日：2016-01-21
申请号：US14755686
申请日：2015-06-30
申请人： Yi-Min Shiu , Chao-Chi Chen , Pei-Sheng Tsu
发明人： Yi-Min Shiu , Chao-Chi Chen , Pei-Sheng Tsu
IPC分类号： H04B3/54
CPC分类号： H04B3/54 , G06F1/26 , G06F13/4282 , G09G2300/0408 , G09G2310/0289 , G11C5/14 , G11C11/4074 , G11C11/4096
摘要： The present invention discloses an input/output (I/O) signal processing circuit and processing method. The I/O signal processing circuit includes a level adjustable I/O circuit and an adjustment circuit. The I/O signal processing circuit includes an output driver and/or an input comparator. The output driver transmits an output signal via a signal transmission line according to an output data. The output driver has an adjustable high operation voltage level and an adjustable low operation voltage level, which determine a high level and a low level of the output signal, respectively. The input comparator receives an input signal via the signal transmission line and comparing the input signal with an adjustable reference voltage, so as to generate an input data. The adjustment circuit generates an adjustment signal according to voltage drop related information, to correspondingly adjust the adjustable high and low operation voltage level and/or the adjustable reference voltage.

14. 发明授权

US06995064B2 Halogen gettering method for forming field effect transistor (FET) device 失效
标题翻译：用于形成场效应晶体管（FET）器件的卤素吸除方法
公开(公告)号：US06995064B2
公开(公告)日：2006-02-07
申请号：US10813786
申请日：2004-03-30
申请人： Ching-Chen Hao , Chao-Chi Chen , Chih-Heng Shen , Chi-Hsun Hsieh
发明人： Ching-Chen Hao , Chao-Chi Chen , Chih-Heng Shen , Chi-Hsun Hsieh
IPC分类号： H01L21/00 , H01L21/84 , H01L21/336
CPC分类号： H01L21/28202 , H01L21/28211 , H01L21/823462 , H01L29/513
摘要： A thermal oxidation method for forming a gate dielectric layer for use within a field effect transistor device employs a thermal oxidizing atmosphere comprising a halogen getter material. By employing the halogen getter material, the field effect transistor device is formed with enhanced performance, in particular with respect to negative bias temperature instability lifetime.
摘要翻译：用于形成在场效应晶体管器件内使用的栅极电介质层的热氧化方法采用包含卤素吸气材料的热氧化气氛。通过采用卤素吸气剂材料，场效晶体管器件形成具有增强的性能，特别是相对于负偏压温度不稳定寿命。

15. 发明授权

US06756291B1 Method for hardening gate oxides using gate etch process 失效
标题翻译：使用栅极蚀刻工艺硬化栅极氧化物的方法
公开(公告)号：US06756291B1
公开(公告)日：2004-06-29
申请号：US10350604
申请日：2003-01-24
申请人： Ching Chen Hao , Jing Chiang Chang , Nai-Chen Lu , Chao-Chi Chen
发明人： Ching Chen Hao , Jing Chiang Chang , Nai-Chen Lu , Chao-Chi Chen
IPC分类号： H01L213205
CPC分类号： H01L21/28202 , H01L21/28061 , H01L21/28176 , H01L21/32137 , H01L29/518
摘要： A method for repairing a damaged gate oxide layer while making the gate oxide layer resistant to gate oxide degradation including providing a silicon substrate having an overlying gate oxide layer and a polysilicon layer overlying the gate oxide layer; forming a polycide layer over the polysilicon layer; photolithographically patterning the polycide layer for dry etching a gate structure; dry etching a gate structure including etching through a thickness of the polycide layer including a fluorine containing etching chemistry to produce implanted fluorine in the polycide layer; and, thermally annealing the silicon substrate including the gate structure to thermally diffuse the implanted fluorine to an interface region of the gate oxide and the silicon substrate to form chemical bonds with silicon.
摘要翻译：一种在使栅极氧化层对栅极氧化物降解有抵抗力的同时修复损坏的栅极氧化物层的方法，包括提供具有覆盖栅极氧化物层的硅衬底和覆盖栅极氧化物层的多晶硅层; 在所述多晶硅层上形成多晶硅化物层; 光刻地图形化多晶硅化物层用于干蚀刻栅极结构; 干蚀刻栅极结构，包括通过包含含氟蚀刻化学品的多晶硅化物层的厚度进行蚀刻以在多晶硅化物层中产生注入的氟; 并且对包括栅极结构的硅基板进行热退火以将注入的氟热扩散到栅极氧化物和硅衬底的界面区域以与硅形成化学键。

16. 发明申请

US20160241304A1 INPUT/OUTPUT SIGNAL PROCESSING CIRCUIT AND INPUT/OUTPUT SIGNAL PROCESSING METHOD 审中-公开
标题翻译：输入/输出信号处理电路和输入/输出信号处理方法
公开(公告)号：US20160241304A1
公开(公告)日：2016-08-18
申请号：US15097240
申请日：2016-04-12
申请人： Yi-Min Shiu , Chao-Chi Chen , Pei-Sheng Tsu
发明人： Yi-Min Shiu , Chao-Chi Chen , Pei-Sheng Tsu
IPC分类号： H04B3/54 , G06F1/26 , G06F13/42
CPC分类号： H04B3/54 , G06F1/26 , G06F13/4282 , G09G2300/0408 , G09G2310/0289 , G11C5/14 , G11C11/4074 , G11C11/4096
摘要： The present invention discloses an input/output (I/O) signal processing circuit and processing method. The I/O signal processing circuit includes a level adjustable I/O circuit and an adjustment circuit. The I/O signal processing circuit includes an output driver and/or an input comparator. The output driver transmits an output signal via a signal transmission line according to an output data. The output driver has an adjustable high operation voltage level and an adjustable low operation voltage level, which determine a high level and a low level of the output signal, respectively. The input comparator receives an input signal via the signal transmission line and comparing the input signal with an adjustable reference voltage, so as to generate an input data. The adjustment circuit generates an adjustment signal according to voltage drop related information, to correspondingly adjust the adjustable high and low operation voltage level and/or the adjustable reference voltage.
摘要翻译：本发明公开了一种输入/输出（I / O）信号处理电路及其处理方法。 I / O信号处理电路包括电平可调I / O电路和调整电路。 I / O信号处理电路包括输出驱动器和/或输入比较器。输出驱动器根据输出数据通过信号传输线传输输出信号。输出驱动器具有可调节的高工作电压电平和可调节的低工作电压电平，分别决定输出信号的高电平和低电平。输入比较器经由信号传输线接收输入信号，并将输入信号与可调参考电压进行比较，以产生输入数据。调整电路根据电压降相关信息生成调整信号，相应地调整可调高低电平操作电压和/或可调参考电压。

17. 发明授权

US08772054B2 Focus control method for photolithography 有权
标题翻译：光刻对焦控制方法
公开(公告)号：US08772054B2
公开(公告)日：2014-07-08
申请号：US13227805
申请日：2011-09-08
申请人： Jen-Pan Wang , Chien-Hsuan Liu , Ching-Hsien Chen , Chao-Chi Chen
发明人： Jen-Pan Wang , Chien-Hsuan Liu , Ching-Hsien Chen , Chao-Chi Chen
IPC分类号： H01L21/66
CPC分类号： G03F7/70641 , G03F7/70341 , G03F9/7026 , G03F9/7034 , G03F9/7053
摘要： A method comprises providing a semiconductor substrate having at least one layer of a material over the substrate. A sound is applied to the substrate, such that a sound wave is reflected by a top surface of the layer of material The sound wave is detected using a sensor. A topography of the top surface is determined based on the detected sound wave. The determined topography is used to control an immersion lithography process.
摘要翻译：一种方法包括提供在衬底上具有至少一层材料的半导体衬底。对基板施加声音，使得声波被材料层的顶表面反射。使用传感器检测声波。基于检测到的声波来确定顶面的形貌。确定的地形用于控制浸没光刻工艺。

18. 发明授权

US08962353B2 System and methods for semiconductor device performance prediction during processing 有权
标题翻译：处理过程中半导体器件性能预测的系统和方法
公开(公告)号：US08962353B2
公开(公告)日：2015-02-24
申请号：US13234964
申请日：2011-09-16
申请人： Jen-Pan Wang , Chao-Chi Chen , Yaling Huang
发明人： Jen-Pan Wang , Chao-Chi Chen , Yaling Huang
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/12
摘要： Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described.
摘要翻译：用于在处理过程中预测半导体器件性能标准的方法和系统。描述了一种包括接收半导体晶片的方法; 在形成有源器件的半导体晶片上执行半导体处理，其在完成时将呈现器件性能标准; 在半导体处理期间，测量至少一个器件性能标准相关的物理参数; 使用所述至少一个在线测量来估计所述有源器件的器件性能标准的估计值，并使用对应于后续半导体处理步骤的器件性能标准相关物理参数的估计测量值; 将设备性能标准的估计值与可接受范围进行比较; 以及基于所述比较来确定所述半导体晶片上的有源器件是否将器件性能标准在可接受的范围内。描述了一种用于处理半导体晶片的系统，其包括用于执行该方法的可编程处理器。

19. 发明申请

US20130071957A1 System and Methods for Semiconductor Device Performance Prediction During Processing 有权
标题翻译：半导体器件性能预测的系统和方法
公开(公告)号：US20130071957A1
公开(公告)日：2013-03-21
申请号：US13234964
申请日：2011-09-16
申请人： Jen-Pan Wang , Chao-Chi Chen , Yaling Huang
发明人： Jen-Pan Wang , Chao-Chi Chen , Yaling Huang
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , H01L22/12
摘要： Methods and systems for predicting semiconductor device performance criteria during processing. A method is described that includes receiving a semiconductor wafer; performing semiconductor processing on the semiconductor wafer forming active devices that, when completed, will exhibit a device performance criteria; during the semiconductor processing, measuring in line at least one device performance criteria related physical parameter; projecting an estimated value for the device performance criteria of the active devices using the at least one in line measurement and using estimated measurements for device performance criteria related physical parameters corresponding to later semiconductor processing steps; comparing the estimated value for the device performance criteria to an acceptable range; and determining, based on the comparing, whether the active devices on the semiconductor wafer will have a device performance criteria within the acceptable range. A system for processing semiconductor wafers that includes a programmable processor for performing the methods is described.
摘要翻译：用于在处理过程中预测半导体器件性能标准的方法和系统。描述了一种包括接收半导体晶片的方法; 在形成有源器件的半导体晶片上执行半导体处理，其在完成时将呈现器件性能标准; 在半导体处理期间，测量至少一个器件性能标准相关的物理参数; 使用所述至少一个在线测量来估计所述有源器件的器件性能标准的估计值，并使用对应于后续半导体处理步骤的器件性能标准相关物理参数的估计测量值; 将设备性能标准的估计值与可接受范围进行比较; 以及基于所述比较来确定所述半导体晶片上的有源器件是否将器件性能标准在可接受的范围内。描述了一种用于处理半导体晶片的系统，其包括用于执行该方法的可编程处理器。

20. 发明申请

US20070117337A1 Method for forming a trench capacitor 有权
标题翻译：形成沟槽电容器的方法
公开(公告)号：US20070117337A1
公开(公告)日：2007-05-24
申请号：US11285449
申请日：2005-11-21
申请人： Chao-Chi Chen , Chuan-Ping Hou
发明人： Chao-Chi Chen , Chuan-Ping Hou
IPC分类号： H01L21/20
CPC分类号： H01L27/1087 , H01L27/10829 , H01L29/945
摘要： A method for forming a trench capacitor is presented in the following process steps. A trench is formed on a semiconductor substrate. A first trench dielectric is deposited into the trench without reaching a full height thereof. An etch stop layer is formed on the first trench dielectric and along inner surfaces of the trench. A second trench dielectric is deposited on the etch stop layer. The second trench dielectric and the etch stop layer are removed to expose the first trench dielectric in the trench. A conductive layer is formed on the first trench dielectric in the trench, such that the conductive layer, the first trench dielectric and the semiconductor substrate function as a trench capacitor.
摘要翻译：用于形成沟槽电容器的方法在以下工艺步骤中呈现。在半导体衬底上形成沟槽。第一沟槽电介质沉积到沟槽中而不达到其整个高度。蚀刻停止层形成在第一沟槽电介质上并且沿着沟槽的内表面。第二沟槽电介质沉积在蚀刻停止层上。去除第二沟槽电介质和蚀刻停止层以暴露沟槽中的第一沟槽电介质。导电层形成在沟槽中的第一沟槽电介质上，使得导电层，第一沟槽电介质和半导体衬底用作沟槽电容器。

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