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11. 发明申请

US20090197394A1 WAFER PROCESSING 有权
公开(公告)号：US20090197394A1
公开(公告)日：2009-08-06
申请号：US12025623
申请日：2008-02-04
申请人： Kunal R. Parekh
发明人： Kunal R. Parekh
IPC分类号： H01L21/00
CPC分类号： H01L21/78
摘要： Methods for processing semiconductor wafers are described herein. One embodiment includes removing portions of a first side of the semiconductor wafer to form a number of trenches of a particular depth in rows and columns. The method further includes forming a passivation layer on side walls of the number of trenches. The method also includes cutting a second side of the semiconductor wafer in rows and columns aligned with the number of trenches such that the semiconductor wafer singulates into a number of dice.

12. 发明授权

US07439138B2 Method of forming integrated circuitry 有权
标题翻译：形成集成电路的方法
公开(公告)号：US07439138B2
公开(公告)日：2008-10-21
申请号：US11497598
申请日：2006-07-31
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L21/00
CPC分类号： H01L21/823468 , H01L21/823418 , H01L21/823425 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.
摘要翻译：本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与靠近晶体管的栅极的各向异性蚀刻的侧壁间隔开。

13. 发明授权

US07419865B2 Methods of forming memory circuitry 有权
标题翻译：形成存储器电路的方法
公开(公告)号：US07419865B2
公开(公告)日：2008-09-02
申请号：US11515648
申请日：2006-09-05
申请人： Kunal R. Parekh , Byron N. Burgess
发明人： Kunal R. Parekh , Byron N. Burgess
IPC分类号： H01L21/8242
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76834 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907
摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.
摘要翻译：本发明包括形成存储器电路的方法。在一个实施方案中，半导体衬底包括一对在其间接收的位节点的字线。在位节点上的绝缘材料内形成位节点接触开口。牺牲性封堵材料形成在一对字线之间的位节点接触开口内。牺牲性封堵材料从一对字线对之间的位节点接触开口移除，并由与位节点电连接的导电材料代替。之后，将导电材料形成为位线。

14. 发明授权

US07378704B2 Semiconductor constructions, and methods of forming semiconductor constructions 有权
标题翻译：半导体结构以及形成半导体结构的方法
公开(公告)号：US07378704B2
公开(公告)日：2008-05-27
申请号：US11377094
申请日：2006-03-16
申请人： Kunal R. Parekh
发明人： Kunal R. Parekh
IPC分类号： H01L27/108
CPC分类号： H01L21/76283 , H01L21/823481 , H01L21/823878 , H01L21/84 , H01L27/1203
摘要： The invention includes methods of incorporating partial SOI into transistor structures. In particular aspects, dielectric material is provided over semiconductor material, and patterned into at least two segments separated by a gap. Additional semiconductor material is then grown over the dielectric material and within the gap. Subsequently, a transistor is formed to comprise source/drain regions within the additional semiconductor material, and to comprise a channel between the source/drain regions. At least one of the source/drain regions is primarily directly over a segment of the dielectric material, and the channel is not primarily directly over any segment of the dielectric material. The invention also includes constructions comprising partial SOI corresponding to segments of dielectric material, and transistors having at least one source/drain region primarily directly over a segment of dielectric material, and a channel that is not primarily directly over any segment of the dielectric material.
摘要翻译：本发明包括将部分SOI并入晶体管结构的方法。在特定方面，电介质材料设置在半导体材料上，并被图案化成由间隙分开的至少两个段。然后在电介质材料上并在间隙内生长附加的半导体材料。随后，形成晶体管以在附加半导体材料内包括源极/漏极区域，并且包括在源极/漏极区域之间的沟道。源极/漏极区域中的至少一个主要直接位于电介质材料的一段上，并且沟道不主要直接位于介电材料的任何部分上方。本发明还包括包括对应于电介质材料段的部分SOI的构造，以及主要直接位于介电材料段上的至少一个源/漏区的晶体管，以及不主要直接位于电介质材料的任何段上的沟道。

15. 发明授权

US07189662B2 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07189662B2
公开(公告)日：2007-03-13
申请号：US10925793
申请日：2004-08-24
申请人： Kunal R. Parekh , Chandra V. Mouli , M. Ceredig Roberts , Fernando Gonzalez
发明人： Kunal R. Parekh , Chandra V. Mouli , M. Ceredig Roberts , Fernando Gonzalez
IPC分类号： H01L21/31
CPC分类号： H01L21/76801 , H01L21/76829 , H01L21/76834 , H01L21/823462 , H01L21/823481 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/785
摘要： The invention includes methods of forming and/or passivating semiconductor constructions. In particular aspects, various oxides of a semiconductor substrate can be formed by exposing semiconductive material of the substrate to deuterium-enriched steam. In other aspects, a semiconductor construction is passivated by subjecting the construction to an anneal at a temperature of greater than or equal to 350° C. while exposing the construction to a deuterium-enriched ambient.
摘要翻译：本发明包括形成和/或钝化半导体结构的方法。在具体方面，半导体衬底的各种氧化物可以通过将衬底的半导体材料暴露于富氘蒸汽来形成。在其他方面，半导体结构通过在大于或等于350℃的温度下对该结构进行退火而钝化，同时将构造暴露于富氘化环境。

16. 发明授权

US07161857B2 Memory redundancy programming 有权
标题翻译：内存冗余编程
公开(公告)号：US07161857B2
公开(公告)日：2007-01-09
申请号：US11299868
申请日：2005-12-12
申请人： Kunal R. Parekh
发明人： Kunal R. Parekh
IPC分类号： G11C29/00
CPC分类号： G11C17/18 , G11C29/789
摘要： A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.
摘要翻译：提供了一种用于执行冗余编程的方法和装置。本发明的系统包括用于执行存储器测试的设备测试单元。该系统还包括可操作地耦合到设备测试单元的存储器件。存储器件包括存取晶体管，其包括电荷捕获区域。在电荷俘获单元中捕获电荷时修改存取晶体管的阈值电压。存储器件还包括存储器元件和与存储器元件相关联的保险丝。响应于修改存取晶体管的阈值电压，熔丝能够进入替代状态。熔丝的状态可用于对存储元件进行编程或解除编程。

17. 发明授权

US07119397B2 Double blanket ion implant method and structure 有权
标题翻译：双层离子注入法和结构
公开(公告)号：US07119397B2
公开(公告)日：2006-10-10
申请号：US10768081
申请日：2004-02-02
申请人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
发明人： Mark Fischer , Charles H. Dennison , Fawad Ahmed , Richard H. Lane , John K. Zahurak , Kunal R. Parekh
IPC分类号： H01L29/06
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28247 , H01L29/6656
摘要： A double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device is disclosed. The method provides a semiconductor substrate with a gate structure formed on its surface Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.
摘要翻译：公开了一种用于在诸如MOSFET访问装置的存储器阵列器件中形成扩散区的双层覆盖离子注入方法。该方法提供了在其表面上形成栅极结构的半导体衬底。接下来，通过第一覆盖离子注入工艺在与沟道区相邻的区域中形成第一对扩散区。第一次毯式离子注入工艺具有第一能级和剂量。该器件经受氧化条件，其在栅极结构上形成氧化的侧壁。在与第一离子注入工艺相同的位置处进行第二覆盖离子注入工艺，向扩散区域添加额外的掺杂剂。第二次毯子离子注入过程具有第二能量水平和剂量。所得到的扩散区域提供了比现有技术的装置更好的静态刷新性能的装置。此外，第一和第二能量水平和剂量基本上低于现有技术单一植入过程中使用的能级和剂量。

18. 发明授权

US07006392B2 Memory redundancy programming 失效
标题翻译：内存冗余编程
公开(公告)号：US07006392B2
公开(公告)日：2006-02-28
申请号：US10764954
申请日：2004-01-26
申请人： Kunal R. Parekh
发明人： Kunal R. Parekh
IPC分类号： G11C7/00
CPC分类号： G11C17/18 , G11C29/789
摘要： A method and apparatus is provided for performing a redundancy programming. The system of the present invention includes a device testing unit for performing a memory test. The system also includes a memory device operatively coupled to the device testing unit. The memory device includes an access transistor that includes a charge trapping area. A threshold voltage of the access transistor is modified upon trapping of charges in the charge trapping unit. The memory device also includes a memory element and a fuse associated with the memory element. The fuse is capable of entering an alternative state in response to modifying the threshold voltage of the access transistor. The state of the fuse may be used to program or de-program the memory element.
摘要翻译：提供了一种用于执行冗余编程的方法和装置。本发明的系统包括用于执行存储器测试的设备测试单元。该系统还包括可操作地耦合到设备测试单元的存储器件。存储器件包括存取晶体管，其包括电荷捕获区域。在电荷俘获单元中捕获电荷时修改存取晶体管的阈值电压。存储器件还包括存储器元件和与存储器元件相关联的保险丝。响应于修改存取晶体管的阈值电压，熔丝能够进入替代状态。熔丝的状态可用于对存储元件进行编程或解除编程。

19. 发明授权

US06921692B2 Methods of forming memory circuitry 失效
公开(公告)号：US06921692B2
公开(公告)日：2005-07-26
申请号：US10615287
申请日：2003-07-07
申请人： Kunal R. Parekh , Byron N. Burgess
发明人： Kunal R. Parekh , Byron N. Burgess
IPC分类号： G11C11/00 , H01L21/60 , H01L21/8234 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76897 , H01L21/76831 , H01L21/76834 , H01L21/76895 , H01L27/10814 , H01L27/10855 , H01L27/10888 , H01L27/10894 , Y10S257/905 , Y10S257/906 , Y10S257/907
摘要： The invention includes methods of forming memory circuitry. In one implementation, a semiconductor substrate includes a pair of word lines having a bit node received therebetween. A bit node contact opening is formed within insulative material over the bit node. Sacrificial plugging material is formed within the bit node contact opening between the pair of word lines. Sacrificial plugging material is removed from the bit node contact opening between the pair of word lines, and it is replaced with conductive material that is in electrical connection with the bit node. Thereafter, the conductive material is formed into a bit line.

20. 发明授权

US06617635B2 Integrated circuit devices having contact and container structures 有权
标题翻译：具有接触和容器结构的集成电路器件
公开(公告)号：US06617635B2
公开(公告)日：2003-09-09
申请号：US10039950
申请日：2001-12-31
申请人： Kunal R. Parekh , John K. Zahurak
发明人： Kunal R. Parekh , John K. Zahurak
IPC分类号： H01L27108
CPC分类号： H01L27/10894 , H01L27/10811 , H01L27/10852 , H01L28/84 , H01L28/90
摘要： Integrated circuitry fabricated using methods for forming contact structures and container structures, as described herein, are provided. The integrated circuitry formed by the methods of the present invention, for example DRAM structures, provide capacitors in containers having sufficiently high storage capacitance for advanced integrated circuit devices. In addition the methods for forming such container capacitors facilitate the formation of contacts structures and provided for the formation of local interconnect structures and electrical contact to each of the structures formed.
摘要翻译：提供了使用如本文所述形成接触结构和容器结构的方法制造的集成电路。通过本发明的方法（例如DRAM结构）形成的集成电路在具有足够高的存储电容的容器中提供用于高级集成电路器件的电容器。此外，用于形成这种容器电容器的方法有助于形成接触结构并且提供用于形成局部互连结构和与形成的每个结构的电接触。

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