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11. 发明授权

US07388790B2 Semiconductor memory device and dynamic latch refresh method thereof 有权
标题翻译：半导体存储器件及其动态锁存刷新方法
公开(公告)号：US07388790B2
公开(公告)日：2008-06-17
申请号：US11510733
申请日：2006-08-28
申请人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
发明人： Hiroshi Maejima , Noboru Shibata , Katsuaki Isobe
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G11C16/0483 , G11C29/70 , G11C29/832 , G11C2211/565 , H01L27/105 , H01L27/115
摘要： A semiconductor integrated circuit device includes dynamic latches, switch circuit, capacitor, first static latch, and first transfer gate. In refreshing data of the dynamic latches, data stored in the first static latch is moved to the second node through the first transfer gate and saved. The data of the dynamic latch is bootstrapped. The bootstrapped data is transferred to the first node to distribute charges, thereby setting the potential of the first node. The set potential is written back to the dynamic latch to refresh it. The saved data of the second node is moved to the first node through the first transfer gate and written back to the first static latch.
摘要翻译：半导体集成电路器件包括动态锁存器，开关电路，电容器，第一静态锁存器和第一传输门。在动态锁存器的刷新数据中，存储在第一静态锁存器中的数据通过第一传送门移动到第二节点并被保存。动态锁存器的数据被自举。自举数据被传送到第一节点以分配费用，从而设置第一节点的电位。设置电位被写回到动态锁存器来刷新它。第二节点的保存数据通过第一传输门移动到第一节点并写回到第一静态锁存器。

12. 发明授权

US08295090B2 Semiconductor memory device capable of reducing chip size 有权
标题翻译：能够减少芯片尺寸的半导体存储器件
公开(公告)号：US08295090B2
公开(公告)日：2012-10-23
申请号：US12817697
申请日：2010-06-17
申请人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
发明人： Katsuaki Isobe , Noboru Shibata , Toshiki Hisada
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C5/025 , G11C16/0483 , G11C16/14 , G11C16/26 , H01L23/528 , H01L27/11519 , H01L27/11524 , H01L27/1157 , H01L29/1095
摘要： According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.
摘要翻译：根据一个实施例，形成在衬底中的第一导电类型的第一阱。第二导电类型的第二阱形成在第一阱中。多个存储单元，多个第一位线选择晶体管和多个第二位线选择晶体管形成在第二阱中，并且多个第一位线选择晶体管和多个第二位线选择晶体管是布置在所述读出放大器的相对于所述多个位线的多个存储单元的一侧。

13. 发明授权

US07760549B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07760549B2
公开(公告)日：2010-07-20
申请号：US12204409
申请日：2008-09-04
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C16/32 , G11C2211/565
摘要： A memory device includes a control circuit which controls a semiconductor region, a first bit line, a second bit line and a source line. The control circuit is comprised of means for making the first bit line floating, after pre-charging the first bit line to a first potential, means for varying the first bit line from the first potential to a third potential by providing a second potential to the second bit line, the semiconductor region and the source line with the first bit line in the floating state, and means for reading data of the first cell transistor to the first bit line, after setting the first bit line to the third potential.
摘要翻译：存储器件包括控制半导体区域，第一位线，第二位线和源极线的控制电路。所述控制电路包括用于在将所述第一位线预充电到第一电位之后使所述第一位线浮置的装置，用于通过向所述第一电位提供第二电位来将所述第一位线从所述第一电位改变到第三电位的装置第二位线，半导体区域和处于浮置状态的第一位线的源极线，以及在将第一位线设置为第三电位之后，将第一单元晶体管的数据读取到第一位线的装置。

14. 发明申请

US20090067255A1 NONVOLATILE SEMICONDUCTOR MEMORY INCLUDING MEMORY CELL FOR STORING MULTILEVEL DATA HAVING TWO OR MORE VALUES 有权
标题翻译：非易失性半导体存储器，包括用于存储具有两个或多个值的多个数据的存储器单元
公开(公告)号：US20090067255A1
公开(公告)日：2009-03-12
申请号：US12204207
申请日：2008-09-04
申请人： Mikio OGAWA , Katsuaki Isobe , Yoshikazu Takeyama , Mitsuaki Honma , Noboru Shibata
发明人： Mikio OGAWA , Katsuaki Isobe , Yoshikazu Takeyama , Mitsuaki Honma , Noboru Shibata
IPC分类号： G11C16/10
CPC分类号： G11C11/5628 , G11C16/0483 , G11C2211/5621
摘要： A write controller performs verification for checking whether each memory cell is on a predetermined verification level. For a memory cell to be written to a voltage level higher than the predetermined verification level, the write controller stores, in first and second latch circuits, the number of times of write to be performed by a write voltage after the verification. Whenever write is performed by the write voltage, the write controller updates the number of times of write stored in the first and second latch circuits. After write is performed the number of times of write by the write voltage, the write controller performs write by an intermediate voltage lower than the write voltage.
摘要翻译：写入控制器执行用于检查每个存储单元是否处于预定验证级别的验证。对于要写入高于预定验证电平的电压电平的存储单元，写入控制器在第一和第二锁存电路中存储在验证之后由写入电压执行的写入次数。无论何时通过写入电压执行写入，写入控制器更新存储在第一和第二锁存电路中的写入次数。在通过写入电压执行写入次数之后，写入控制器通过低于写入电压的中间电压来执行写入。

15. 发明授权

US07656225B2 Voltage generation circuit and semiconductor memory device including the same 有权
标题翻译：电压产生电路和包括其的半导体存储器件
公开(公告)号：US07656225B2
公开(公告)日：2010-02-02
申请号：US11739397
申请日：2007-04-24
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： G11C7/14 , G11C5/147
摘要： A voltage generation circuit comprises a reference voltage generation circuit; a differential amplifier; an output node; a P-channel MOS transistor; a first resistor series; a second resistor series; a third resistor series; and a selection control circuit. A reference voltage generated by the reference voltage generation circuit is input to a first input terminal of the differential amplifier. The first resistor series is connected between a drain of the P-channel MOS transistor and the output node. The second resistor series is connected between the output node and a second input terminal of the differential amplifier. The third resistor array is connected between the second input terminal of the differential amplifier and a ground. The selection control circuit controls such that a sum of the resistances of the first resistor series and the second resistor series is constant.
摘要翻译：电压产生电路包括参考电压产生电路; 差分放大器; 输出节点; P沟道MOS晶体管; 第一个电阻器系列; 第二个电阻器系列; 第三电阻器系列; 和选择控制电路。由参考电压产生电路产生的参考电压被输入到差分放大器的第一输入端。第一个电阻器系列连接在P沟道MOS晶体管的漏极和输出节点之间。第二电阻器系列连接在差分放大器的输出节点和第二输入端子之间。第三电阻阵列连接在差分放大器的第二输入端和地之间。选择控制电路控制使得第一电阻器系列和第二电阻器系列的电阻之和恒定。

16. 发明授权

US07505314B2 Semiconductor storage device provided with memory cell having charge accumulation layer and control gate 有权
标题翻译：设置有具有电荷累积层和控制栅极的存储单元的半导体存储装置
公开(公告)号：US07505314B2
公开(公告)日：2009-03-17
申请号：US11770199
申请日：2007-06-28
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C11/5635 , G11C16/12 , G11C16/16 , G11C16/3418
摘要： A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.
摘要翻译：半导体存储器件包括存储单元晶体管，第一选择晶体管和字线。每个存储单元晶体管具有包括电荷累积层和控制栅极的堆叠栅极，并且被配置为根据阈值电压保持至少两个级别的“0”数据和“1”数据。对应于“0”数据的阈值电压是由每个存储单元晶体管保持的电平中的最低阈值电压。第一选择晶体管具有与存储单元晶体管之一串联连接的电流通路。每个字线连接到存储单元晶体管之一的控制栅极。保持“0”数据的存储单元晶体管的阈值电压的上限值在每个字线中彼此不同。

17. 发明申请

US20090067245A1 SEMICONDUCTOR MEMORY DEVICE PROVIDED WITH MOS TRANSISTOR HAVING CHARGE ACCUMULATION LAYER AND CONTROL GATE AND DATA WRITE METHOD OF NAND FLASH MEMORY 失效
标题翻译：具有带电荷累积层的MOS晶体管和NAND闪存的控制门和数据写入方法的半导体存储器件
公开(公告)号：US20090067245A1
公开(公告)日：2009-03-12
申请号：US12208798
申请日：2008-09-11
申请人： Katsuaki Isobe , Noboru Shibata
发明人： Katsuaki Isobe , Noboru Shibata
IPC分类号： G11C16/04 , G11C16/06 , G11C8/08
CPC分类号： G11C16/0483 , G11C8/08 , G11C11/5628 , G11C16/10 , G11C2211/565
摘要： A semiconductor memory device includes a memory cell group, a selection transistor, a page buffer, and a row decoder. The memory cell group includes memory cell transistors connected in series. The selection transistor is connected to the memory cell transistor. The page buffer is adopted to apply first and second voltages to the bit lines connected to the memory cell transistors in which the “0” data and “1” data is to be programmed respectively, when the selection transistor is turned on, in a write operation. The page buffer is adopted to put the bit line into electrically floating after the first voltage and the second voltage are applied. The row decoder is adopted to apply a third voltage to a semiconductor layer on which the memory cell transistors are formed, and apply a program voltage to the selected word line when the bit line is in the electrically floating.
摘要翻译：半导体存储器件包括存储单元组，选择晶体管，页缓冲器和行解码器。存储单元组包括串联连接的存储单元晶体管。选择晶体管连接到存储单元晶体管。采用页缓冲器将第一和第二电压施加到连接到存储单元晶体管的位线，其中当写选择晶体管导通时，分别对“0”数据和“1”数据进行编程操作。在施加第一电压和第二电压之后，采用页面缓冲器将位线置于电浮置中。采用行解码器将第三电压施加到其上形成有存储单元晶体管的半导体层，并且当位线处于电浮置时将编程电压施加到所选择的字线。

18. 发明授权

US08315110B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US08315110B2
公开(公告)日：2012-11-20
申请号：US13315967
申请日：2011-12-09
申请人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
发明人： Hideo Mukai , Hiroshi Maejima , Katsuaki Isobe
IPC分类号： G11C7/10
摘要： A nonvolatile-semiconductor-memory-device including a cell array having a plurality of MATs (unit-cell-array) disposed in a matrix, the MATs each include a plurality of first lines, a plurality of second lines crossing the first lines, and memory cells being connected between the first and second lines. The device further includes a first and second drive circuit selecting the first and second lines connected to the memory cells of each MAT that are accessed, and driving the selected first and second lines to write or read data. The memory cells form a page by being connected to each first line selected from the MATs. The device also includes a data latch latching the write or the read data in units of pages, where the first and second drive circuit drive the first and second lines multiple times to write or read data for one page in and out of the cell array.

19. 发明申请

US20110235417A1 NAND FLASH MEMORY 审中-公开
标题翻译： NAND闪存
公开(公告)号：US20110235417A1
公开(公告)日：2011-09-29
申请号：US13154522
申请日：2011-06-07
申请人： Katsuaki Isobe
发明人： Katsuaki Isobe
IPC分类号： G11C16/02
CPC分类号： G11C8/08 , G11C8/10 , G11C16/0483
摘要： A NAND flash memory that is read while a selected bit line and a non-selected bit line are adjacent to each other, has a memory cell array having a plurality of blocks each of which is composed of a plurality of memory cell units, each of said memory cell units having a plurality of electrically rewritable memory cells that are connected to each other and composed of a p-type well surrounded by an n-type well formed in a p-type semiconductor substrate, drain-side select gate transistors each of which connects a memory cell unit to a bit line and is connected to a drain-side select gate line at the gate thereof, and source-side select gate transistors each of which connects a memory cell unit to a source line and is connected to a source-side select gate line at the gate thereof; a row decoder that is connected to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array, and applies a signal voltage to word lines, the drain-side select gate lines and the source-side gate line of said memory cell array for selecting a block; and a sense amplifier that is controlled by a column decoder and makes a selection from said bit lines of said memory cell array, wherein, in a block that is not selected by said row decoder, said bit line selected by said sense amplifier is charged in a state where the drain-side select gate line, the source-side select gate line and the p-type semiconductor substrate are set at a ground potential, and the source lines, the n-type wells, the p-type wells and a bit line that is not selected by said sense amplifier are in a floating state.
摘要翻译：在选择的位线和非选择的位线彼此相邻时读取的NAND快闪存储器具有存储单元阵列，其具有多个块，每个块由多个存储单元单元组成，每个块由多个存储单元单元组成所述存储单元具有多个电可重写存储单元，它们彼此连接并且由形成在p型半导体衬底中的n型阱围绕的p型阱组成，每个漏极侧选择栅晶体管其将存储单元单元连接到位线并连接到其栅极处的漏极侧选择栅极线，以及源极选择栅极晶体管，每个源极选择栅极晶体管将存储单元单元连接到源极线并连接到源极选择栅极线; 连接到所述存储单元阵列的字线，漏极侧选择栅极线和源极侧栅极线的行解码器，并将信号电压施加到字线，漏极侧选择栅极线和源极侧选择栅极线，所述存储单元阵列的侧栅极线用于选择块; 以及由列解码器控制并从所述存储单元阵列的所述位线进行选择的读出放大器，其中，在未被所述行解码器选择的块中，由所述读出放大器选择的所述位线被充电漏极侧选择栅极线，源极侧选择栅极线和p型半导体衬底设置为接地电位的状态，源极线，n型阱，p型阱和a 未被所述读出放大器选择的位线处于浮置状态。

20. 发明申请

US20110134695A1 SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：半导体存储器件
公开(公告)号：US20110134695A1
公开(公告)日：2011-06-09
申请号：US12957865
申请日：2010-12-01
申请人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
发明人： Kazushige Kanda , Toshiki Hisada , Katsuaki Isobe
IPC分类号： G11C16/04
CPC分类号： H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： Provided is a semiconductor memory device including: multiple bit lines arranged in parallel to one another; multiple sense-amplifier bit lines arranged away from end portions of the bit lines; a fourth sense-amplifier bit line formed with a wire of a first layer arranged below the bit lines; selection transistors with a pair of gate electrodes arranged in a direction normal to the first to sixth bit lines; a first wire arranged below the bit lines and the sense-amplifier bit lines, and having an end portion extending to below the third bit line and connected to the bit line; a third wire formed with a layer of the gate electrode used as a wire, the third wire including a first end portion positioned below the fourth sense-amplifier bit line and connected to the fourth sense-amplifier bit line, and a second end portion positioned below the second sense-amplifier bit line; and a fourth wire formed with a wire of the first layer and arranged between the third wire and the second sense-amplifier bit line to connect the third wire to the second sense-amplifier bit line.
摘要翻译：提供一种半导体存储器件，包括：彼此平行布置的多个位线; 多个读出放大器位线布置成远离位线的端部; 第四感测放大器位线，其布置在位线下方的第一层的导线; 选择晶体管，其具有沿与第一至第六位线垂直的方向排列的一对栅电极; 布置在位线下方的第一线和读出放大器位线，并且具有延伸到第三位线下方并连接到位线的端部; 第三线，其形成有用作线的栅极电极层，所述第三线包括位于所述第四感测放大器位线下方并连接到所述第四感测放大器位线的第一端部，以及位于低于第二感测放大器位线; 以及第四导线，其由第一层的导线形成，并且布置在第三导线和第二读出放大器位线之间，以将第三导线连接到第二感测放大器位线。

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