专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

WO2008048690A2 FORWARD DECISION AIDED NONLINEAR VITERBI DETECTOR 审中-公开
标题翻译：前瞻性决定非线性VITERBI检测器
公开(公告)号：WO2008048690A2
公开(公告)日：2008-04-24
申请号：PCT/US2007/022412
申请日：2007-10-18
申请人： MARVELL WORLD TRADE LTD. , YANG, Shaohua , WU, Zining
发明人： YANG, Shaohua , WU, Zining
CPC分类号： H03M13/4169 , G11B20/10009 , G11B20/10296 , H03M13/3961 , H03M13/41 , H03M13/6502
摘要： A system, apparatus, and method are provided for a nonlinear Viterbi detector that may be used in an iterative decoding system or any other system with multiple, interconnected detectors. At least one of the Viterbi detectors may estimate the digital information sequence in a received signal based on the signal itself and an estimate of the signal from another of the Viterbi detectors. The at least one Viterbi detector may calculate branch metrics for a subset of the branches in an associated trellis diagram by selecting branches that correspond to the output of the other Viterbi detector. Thus, the area and complexity of the at least one Viterbi detector may be reduced approximately two-fold or more.
摘要翻译：提供了一种用于非线性维特比检测器的系统，装置和方法，其可用于迭代解码系统或具有多个互连检测器的任何其它系统。维特比检测器中的至少一个可以基于信号本身估计接收信号中的数字信息序列，并且估计来自另一个维特比检测器的信号。所述至少一个维特比检测器可以通过选择与其他维特比检测器的输出相对应的分支来计算相关网格图中的分支子集的分支度量。因此，至少一个维特比检测器的面积和复杂度可以减小大约两倍或更多。

12. 发明申请

WO2016032817A1 STORAGE DEVICE CONTROLLER ARCHITECTURE 审中-公开
标题翻译：存储设备控制器架构
公开(公告)号：WO2016032817A1
公开(公告)日：2016-03-03
申请号：PCT/US2015/045872
申请日：2015-08-19
申请人： MARVELL WORLD TRADE LTD. , WU, Zining
发明人： WU, Zining
IPC分类号： G06F3/06
CPC分类号： G06F3/0647 , G06F3/061 , G06F3/0626 , G06F3/0658 , G06F3/067 , G06F3/0683 , G06F3/0688 , G06F11/073 , G06F11/0793
摘要： Data storage apparatus includes a plurality of drive units, each of the drive units including a plurality of memory channels, and a plurality of storage medium controllers. Each storage medium controller addresses at least one of the memory channels. Each of the storage medium controllers is incapable of performing file system operations. An integrated storage controller connected to each of the drive units performs all file system operations of the data storage apparatus. The integrated storage controller includes a central processing unit, a host interface, and at least one storage medium interface for communicating with the plurality of storage medium controllers. A method for operating such data storage apparatus includes performing, in the integrated storage controller, error correction across all of the memory channels, as well as redundancy and wear-leveling. Each storage medium controller may perform error correction across all of the memory channels addressed by that controller.
摘要翻译：数据存储装置包括多个驱动单元，每个驱动单元包括多个存储器通道，以及多个存储介质控制器。每个存储介质控制器寻址至少一个存储器通道。每个存储介质控制器都不能执行文件系统操作。连接到每个驱动单元的集成存储控制器执行数据存储装置的所有文件系统操作。集成存储控制器包括中央处理单元，主机接口和用于与多个存储介质控制器进行通信的至少一个存储介质接口。用于操作这种数据存储装置的方法包括在集成存储控制器中执行跨所有存储器通道的错误校正，以及冗余和磨损均衡。每个存储介质控制器可以在由该控制器寻址的所有存储器通道上执行纠错。

13. 发明申请

WO2008147980A2 MULTI-MODE AUDIO AMPLIFIERS 审中-公开
标题翻译：多模音频放大器
公开(公告)号：WO2008147980A2
公开(公告)日：2008-12-04
申请号：PCT/US2008/064685
申请日：2008-05-23
申请人： MARVELL WORLD TRADE LTD. , WU, Zining
发明人： WU, Zining
IPC分类号： H03F3/181 , H03H17/02
CPC分类号： H03H17/0294 , H03F3/217 , H03F2200/03 , H03F2200/351 , H03H17/06 , H03H2220/08
摘要： A multimode audio amplifier comprises: a mode controller adapted to provide a control signal; and at least one multimode module, wherein each of the multimode modules has a plurality of operating modes, wherein the operating modes are selected in accordance with the control signal, wherein changing the operating modes results in a measurable change in at least one characteristic of the multimode audio amplifier; wherein the characteristics of the multimode audio amplifier consist of signal to noise ratio (SNR); total harmonic distortion and noise (THD+N); input to output delay; power consumption; and efficiency.
摘要翻译：多模音频放大器包括：模式控制器，适于提供控制信号; 以及至少一个多模模块，其中每个多模模块具有多个操作模式，其中根据控制信号选择操作模式，其中改变操作模式导致至少一个特征的可测量的变化多模音频放大器; 其中多模音频放大器的特性由信噪比（SNR）组成; 总谐波失真和噪声（THD + N）; 输入到输出延迟; 能量消耗; 和效率。

14. 发明申请

WO2008036378A2 RELIABILITY METRIC GENERATION FOR TRELLIS-BASED DETECTION AND/OR DECODING 审中-公开
标题翻译：基于TRLLIS的检测和/或解码的可靠性公制生成
公开(公告)号：WO2008036378A2
公开(公告)日：2008-03-27
申请号：PCT/US2007/020423
申请日：2007-09-20
申请人： MARVELL WORLD TRADE LTD. , YANG, Shaohua , LOW, Seo-How , WU, Zining , BURD, Gregory
发明人： YANG, Shaohua , LOW, Seo-How , WU, Zining , BURD, Gregory
IPC分类号： H03M13/41
CPC分类号： H03M13/4153 , H03M13/098 , H03M13/2933 , H04L25/03203 , H04L25/067
摘要： The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology computes soft reliability information for each detected/decoded bit or codeword syndrome value.
摘要翻译：所公开的技术提供用于识别与基于网格的检测/解码相关的潜在错误位置，模式和似然度量的系统和方法。在本发明的一个方面，所公开的技术为每个检测/解码的比特或码字综合征值计算软可靠性信息。

15. 发明申请

WO2007109262A3 METHOD AND APPARATUS FOR GENERATING NON-BINARY BALANCED CODES 审中-公开
公开(公告)号：WO2007109262A3
公开(公告)日：2007-09-27
申请号：PCT/US2007/006900
申请日：2007-03-20
申请人： MARVELL WORLD TRADE LTD. , CHAICHANAVONG, Panue , WU, Zining
发明人： CHAICHANAVONG, Panue , WU, Zining
IPC分类号： H04L25/49
摘要： An encoder and method of decoding includes a grouping module that groups an input signal into a plurality of blocks, wherein the plurality of blocks include a current block and at least one prior block, wherein each of the plurality of blocks includes at least N symbols, and wherein each of the N symbols has one of q symbol values, where N is a positive integer and q is an integer greater than two. The encoder further includes a counting module that counts occurrences of the q symbol values in the at least one prior block to generate a first count and occurrences of the q symbol values in the current block to generate a second count. The encoder also includes a permutation module that selectively permutes the current block based on the first and second counts.

16. 发明申请

WO2007103317A1 SYSTEMS AND METHODS FOR ACHIEVING HIGHER CODING RATE USING PARITY INTERLEAVING 审中-公开
标题翻译：使用奇偶校验交互实现更高编码率的系统和方法
公开(公告)号：WO2007103317A1
公开(公告)日：2007-09-13
申请号：PCT/US2007/005602
申请日：2007-03-05
申请人： MARVELL WORLD TRADE LTD. , TANG, Heng , BURD, Gregory , WU, Zining , CHAICHANAVONG, Panu
发明人： TANG, Heng , BURD, Gregory , WU, Zining , CHAICHANAVONG, Panu
IPC分类号： H03M5/14
CPC分类号： G11B20/1423 , H03M5/145
摘要： The disclosed technology provides systems and methods for encoding data based on a run-length-limited code and an error correction code to provide codewords. The codewords include RLL-encoded data that are produced based on the RLL code, and parity information that are produced based on the error correction code. The parity information is interleaved among the RLL-encoded data. In one embodiment, the codeword is produced by separately producing the RLL-encoded data and the parity information, and interleaving the parity information among the RLL-encoded data. In one embodiment, the codeword is produced by producing the RLL-encoded data, and using erasure decoding the compute the parity information.
摘要翻译：所公开的技术提供了用于基于游程长度限制代码和纠错码来编码数据以提供码字的系统和方法。码字包括基于RLL码产生的RLL编码数据和基于纠错码产生的奇偶校验信息。奇偶校验信息在RLL编码数据之间进行交织。在一个实施例中，通过分别产生RLL编码数据和奇偶校验信息，以及在RLL编码数据之间交织奇偶校验信息来产生码字。在一个实施例中，通过产生RLL编码数据产生码字，并且使用擦除解码来计算奇偶校验信息。

17. 发明授权

EP1987519B1 METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY 有权转让
标题翻译：方法和系统纠错闪存
公开(公告)号：EP1987519B1
公开(公告)日：2015-08-19
申请号：EP07718293.9
申请日：2007-01-19
申请人： Marvell World Trade Ltd.
发明人： RAMAMOORTHY, Aditya , WU, Zining , SUTARDJA, Pantas
IPC分类号： G06F11/10 , G11C27/00 , G11C11/56 , G11C7/10
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.

18. 发明公开

EP1987519A2 METHOD AND SYSTEM FOR ERROR CORRECTION IN FLASH MEMORY 有权转让
标题翻译：方法和系统纠错闪存
公开(公告)号：EP1987519A2
公开(公告)日：2008-11-05
申请号：EP07718293.9
申请日：2007-01-19
申请人： Marvell World Trade Ltd.
发明人： RAMAMOORTHY, Aditya , WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G06F11/1068 , G06F11/1072 , G06F11/1666 , G06F2212/403 , G11C7/02 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C16/10 , G11C27/005 , G11C29/00 , G11C2029/0411 , G11C2207/16 , G11C2211/562 , G11C2211/563 , H03M13/1177 , H03M13/1515
摘要： A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.

19. 发明公开

EP3054595A1 PULSE WIDTH MODULATION 审中-公开
标题翻译： PULSWEITENMODULATION
公开(公告)号：EP3054595A1
公开(公告)日：2016-08-10
申请号：EP16154780.7
申请日：2016-02-09
申请人： Marvell World Trade Ltd.
发明人： JAIN, Kapil , WU, Zining
IPC分类号： H03K7/08
CPC分类号： H03K7/08
摘要： A device includes a combining circuitry that receives an incoming signal, and one or more delayed signals from a delay circuitry. The combining circuitry combines the incoming signal and the one or more delayed signals to generate a combined signal. The device includes a comparing circuitry that receives the combined signal from the combining circuitry, and compares a pulse width of the combined signal to a threshold pulse width. When the pulse width of the combined signal is greater than or equal to the threshold pulse width, the comparing circuitry provides the combined signal to an amplifier circuit and provides a null signal to the delay circuitry. The amplifier circuit generates a pulse width modulated (PWM) signal based on the combined signal.
摘要翻译：一种装置包括接收输入信号的组合电路和来自延迟电路的一个或多个延迟信号。组合电路组合输入信号和一个或多个延迟信号以产生组合信号。该装置包括比较电路，其接收来自组合电路的组合信号，并将组合信号的脉冲宽度与阈值脉冲宽度进行比较。当组合信号的脉冲宽度大于或等于阈值脉冲宽度时，比较电路将组合信号提供给放大器电路，并向延迟电路提供零信号。放大器电路基于组合信号产生脉宽调制（PWM）信号。

20. 发明授权

EP1984923B1 FLASH MEMORY WITH CODING AND SIGNAL PROCESSING 有权转让
标题翻译：与编码和信号处理闪存
公开(公告)号：EP1984923B1
公开(公告)日：2013-08-14
申请号：EP07718319.2
申请日：2007-01-19
申请人： Marvell World Trade Ltd.
发明人： WU, Zining , SUTARDJA, Pantas
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G06F11/1072 , G06F11/1068 , G11C7/1006 , G11C7/16 , G11C11/56 , G11C29/00 , G11C2029/0411 , G11C2211/5641

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式