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11. 发明授权

US08098567B2 Timing adjustments for channel estimation in a multi carrier system 有权
标题翻译：多载波系统中信道估计的时序调整
公开(公告)号：US08098567B2
公开(公告)日：2012-01-17
申请号：US11777251
申请日：2007-07-12
申请人： Matthias Brehler , Joseph Chan
发明人： Matthias Brehler , Joseph Chan
IPC分类号： H04J11/00
CPC分类号： H04L27/2695 , H04L5/0007 , H04L5/0048 , H04L27/2665
摘要： Apparatus and methods are provided for making timing adjustments in a multi carrier communications system. In an aspect, a timing correction method is provided for a multi-carrier system. This includes adjusting the time basis of two or more pilot interlaces with respect to each other in order to account for timing differences between the interlaces when combining the interlaces, and then adjusting or matching the time bases of the combined interlaces with a symbol to be demodulated. The alignment and matching is performed in order to generate channel estimates for data demodulation. The channel estimates, thus generated, along with the timing alignment information are in turn used for determining timing corrections to be applied to demodulation of a particular symbol. Corresponding apparatus are also disclosed that implement the methodology.
摘要翻译：提供了用于在多载波通信系统中进行时序调整的装置和方法。在一方面，为多载波系统提供定时校正方法。这包括相对于彼此调整两个或多个导频交织的时间基准，以便在组合交织时考虑交织之间的定时差，然后将组合交织的时基与要解调的符号进行调整或匹配。执行对准和匹配以便产生用于数据解调的信道估计。由此产生的信道估计与定时对准信息一起用于确定要应用于特定符号的解调的定时校正。还公开了实现该方法的相应装置。

12. 发明申请

US20070164365A1 SINGLE STRESS LINER FOR MIGRATION STABILITY AND SPEED 审中-公开
标题翻译：用于移动稳定性和速度的单应力衬管
公开(公告)号：US20070164365A1
公开(公告)日：2007-07-19
申请号：US11306943
申请日：2006-01-17
申请人： Joseph Chan , Robert Wong
发明人： Joseph Chan , Robert Wong
IPC分类号： H01L29/94
CPC分类号： H01L27/1104 , H01L29/7843
摘要： A single stress liner is applied over different type semiconductor devices. The single stress liner avoids the problems of a dual/hybrid stress liner scheme by eliminating the meeting area. The single stress liner may be tensile or compressive. In one embodiment, the semiconductor device includes a static random access memory (SRAM) cell having numerous NFETs and PFETs. In this case, a compressive liner is placed over the SRAM cell, which is normally not ideal for the NFETs therein, but is desirable for the SRAM cell because continued miniaturization of the SRAMs typically requires slowing of the NFETs for the SRAM to maintain stabile. Where SRAM cells require increased speed, a single tensile stress liner can be implemented.
摘要翻译：单个应力衬垫施加在不同类型的半导体器件上。单应力衬垫通过消除会议面积避免双重/混合应力衬垫方案的问题。单个应力衬垫可以是拉伸或压缩的。在一个实施例中，半导体器件包括具有许多NFET和PFET的静态随机存取存储器（SRAM）单元。在这种情况下，压电衬垫放置在SRAM单元上，这对于其中的NFET通常不是理想的，但是对于SRAM单元来说是理想的，因为SRAM的继续小型化通常需要NSTS缓慢以使SRAM保持稳定。在SRAM单元需要增加速度的情况下，可以实现单个拉伸应力衬垫。

13. 发明申请

US20070159359A1 Method and apparatus for handling signpost signals in a tag 有权
标题翻译：用于处理标签中的路标信号的方法和装置
公开(公告)号：US20070159359A1
公开(公告)日：2007-07-12
申请号：US11329411
申请日：2006-01-10
申请人： Nikola Cargonja , Joseph Chan , Don Ahn , Neal Herman
发明人： Nikola Cargonja , Joseph Chan , Don Ahn , Neal Herman
IPC分类号： G08G1/123 , G08B13/14
CPC分类号： G07C9/00111 , G07C5/008
摘要： A tag stores information identifying the sequence in which it received wireless signpost signals from different signposts. In another configuration, a tag maintains data identifying a group of signposts that are to be treated as equivalent. In yet another configuration, wireless signpost signals transmitted by each of a plurality of signposts all contain the same signpost code. In still another configuration, a signpost has an interface through which a signpost code of the signpost can be selectively set.
摘要翻译：标签存储识别从不同路标接收到无线路标信号的序列的信息。在另一个配置中，标签维护标识要被视为等效的一组路标的数据。在另一种配置中，由多个路标中的每一个发送的无线路标信号都包含相同的路标代码。在另一个配置中，路标具有可以选择性地设置路标的路标代码的接口。

14. 发明申请

US20060267555A1 Method and apparatus for detecting a battery voltage 有权
标题翻译：用于检测电池电压的方法和装置
公开(公告)号：US20060267555A1
公开(公告)日：2006-11-30
申请号：US11140586
申请日：2005-05-27
申请人： Nikola Cargonja , Joseph Chan , Don Ahn
发明人： Nikola Cargonja , Joseph Chan , Don Ahn
IPC分类号： H02J7/00
CPC分类号： H02J7/0047 , G01R19/16542 , G01R31/3648 , G01R31/3675
摘要： One aspect of the invention involves: maintaining a record of how long a circuit operates in each of a plurality of different operating modes thereof, starting from a point in time at which a battery that powers the circuit is replaced; calculating for each of the operating modes as a function of the record a cumulative current drain from the point in time to a current time; and determining as a function of the cumulative current drains whether the battery is subject to a low voltage condition. Another aspect involves: monitoring a voltage of a battery; periodically determining whether the voltage of the battery is subject to a low voltage condition; and maintaining a count of the number of times that the determining results in a determination that the battery is subject to a low voltage condition.
摘要翻译：本发明的一个方面涉及：从更换电路供电的电池的时间点开始，保持电路在多种不同工作模式中的每一种中工作多长时间的记录; 根据记录从时间点到当前时间的累积电流消耗来计算每个工作模式; 以及确定电池是否经受低电压状态的累积电流消耗的函数。另一方面涉及：监测电池的电压; 周期性地确定电池的电压是否经历低电压状态; 并且保持所述确定导致电池处于低电压状态的确定的次数的计数。

15. 发明授权

US06411665B1 Phase locked loop clock extraction 失效
标题翻译：锁相环时钟提取
公开(公告)号：US06411665B1
公开(公告)日：2002-06-25
申请号：US09268523
申请日：1999-03-11
申请人： Joseph Chan , Richard Francis Bastable
发明人： Joseph Chan , Richard Francis Bastable
IPC分类号： H03K1900
CPC分类号： H03L7/087 , H03L7/0895 , H03L7/113 , H04L7/033
摘要： A clock recovery circuit includes a phase locked loop in which the control voltage of a voltage controlled oscillator is controlled by a loop filter driven by the output of a phase comparator. During acquisition of the phase locked condition, a frequency error detector is used to detect frequency error and input a frequency error signal to a charge pump circuit associated with the loop filter. Frequency error is detected by a method of determining the phase quadrant of clock signal in which each transition of the data occurs, an algorithm implemented by logic circuit being utilized to selectively generate the frequency error signal only for certain defined transitions between phase quadrant values. Sampling of the phase quadrant values is effected by sampling sub-circuits using latched values of the clock and quadrature clock signals to obtain samples of the clock and quadrature clock signals for each transition, and subsequently determining the phase quadrant value by a logical combination of the samples. The method and apparatus have application in data recovery in optical communications systems operating in the GHz range.
摘要翻译：时钟恢复电路包括锁相环，其中压控振荡器的控制电压由相位比较器的输出驱动的环路滤波器控制。在获取锁相条件期间，使用频率误差检测器来检测频率误差，并将频率误差信号输入到与环路滤波器相关的电荷泵电路。通过确定数据发生的每个转换的时钟信号的相位象限的方法来检测频率误差，由逻辑电路实现的算法被用于仅针对相位象限值之间的某些定义的转换选择性地产生频率误差信号。相位象限值的采样通过使用锁存的时钟和正交时钟信号的值对子电路进行采样，以获得用于每个转换的时钟和正交时钟信号的采样，随后通过逻辑组合确定相位象限值样品。该方法和装置可用于在GHz范围内工作的光通信系统中的数据恢复。

16. 外观设计

USD427173S Telephone base 失效
公开(公告)号：USD427173S
公开(公告)日：2000-06-27
申请号：US77061
申请日：1997-09-25
申请人： Joseph Chan , Steve Hughes , Andrew Jones , Stascha Offenbeck
设计人： Joseph Chan , Steve Hughes , Andrew Jones , Stascha Offenbeck

17. 发明授权

US6002269A TTL logic driver circuit 失效
标题翻译： TTL逻辑驱动电路
公开(公告)号：US6002269A
公开(公告)日：1999-12-14
申请号：US996866
申请日：1997-12-23
申请人： Peter Dartnell , Joseph Chan
发明人： Peter Dartnell , Joseph Chan
IPC分类号： H03K19/013 , H03K19/018 , H03K19/0175 , H03K19/082
CPC分类号： H03K19/01806 , H03K19/0133
摘要： A bootstrap logic driver circuit operable from a low voltage power supply includes first and second bipolar transistors coupled between positive and negative voltage supplies and having a collector load comprising a first diode structure. A further transistor coupled between the voltage supplies has a collector load comprising a second diode structure. A bootstrap capacitor coupled between the diode structures stores charge when the circuit is in a first condition and is discharged when the circuit is in a second condition to provide an enhanced drive voltage for an output transistor.
摘要翻译：可从低电压电源工作的自举逻辑驱动器电路包括耦合在正电压和负电压源之间并具有包含第一二极管结构的集电极负载的第一和第二双极晶体管。耦合在电压源之间的另一个晶体管具有包括第二二极管结构的集电极负载。耦合在二极管结构之间的自举电容器在电路处于第一状态时存储电荷，并且当电路处于第二状态时放电，以为输出晶体管提供增强的驱动电压。

18. 外观设计

USD408405S Telephone handset 失效
公开(公告)号：USD408405S
公开(公告)日：1999-04-20
申请号：US63021
申请日：1996-11-22
申请人： Joseph Chan
设计人： Joseph Chan

19. 发明授权

US5640043A High voltage silicon diode with optimum placement of silicon-germanium layers 失效
标题翻译：具有硅 - 锗层最佳放置的高压硅二极管
公开(公告)号：US5640043A
公开(公告)日：1997-06-17
申请号：US580071
申请日：1995-12-20
申请人： Jack Eng , Joseph Chan , Lawrence Laterza , Gregory Zakaluk , Jun Wu , John Amato , Dennis Garbis , Willem Einthoven
发明人： Jack Eng , Joseph Chan , Lawrence Laterza , Gregory Zakaluk , Jun Wu , John Amato , Dennis Garbis , Willem Einthoven
IPC分类号： H01L21/205 , H01L29/165 , H01L29/861 , H01L29/06 , H01L27/082
CPC分类号： H01L29/165 , H01L29/8613
摘要： A high voltage silicon rectifier includes a substrate portion and an epitaxial mesa portion that is a frustrum of a pyramid with a substantially square cross section and side walls that make a forty five degree angle with the substrate portion. The mesa portion includes three germanium doped layers that introduce strain to speed up recombination of charge carriers. The topography of the base region of the rectifier has a high-low junction that includes a central portion that is deeper in the mesa than the germanium-doped layers and an edge portion that is shallower in the mesa than the germanium-doped layers and forms a positive bevel angle with the tapered side walls of the mesa,
摘要翻译：高压硅整流器包括基板部分和外延台面部分，该外延台面部分是具有基本上正方形横截面的金字塔的棱角，并且与基板部分成四十五度的角。台面部分包括三个锗掺杂层，其引入应变以加速电荷载体的复合。整流器的基极区域的形貌具有高低结，其包括在台面比锗掺杂层更深的中心部分和在台面比锗掺杂层更浅的边缘部分与台面的锥形侧壁呈正斜角，

20. 发明授权

US06909320B2 Method and apparatus for dual output voltage regulation 有权
标题翻译：双输出电压调节方法和装置
公开(公告)号：US06909320B2
公开(公告)日：2005-06-21
申请号：US10465753
申请日：2003-06-19
申请人： Joseph Chan , Dennis Cashen
发明人： Joseph Chan , Dennis Cashen
IPC分类号： G05F3/24 , G05F1/10
CPC分类号： G05F3/24
摘要： A dual output voltage regulator circuit includes a first voltage regulator section, the first voltage regulator section having a first regulated voltage output, a second voltage regulator section coupled to the first voltage regulator section, the second voltage regulator having a second regulated voltage output, and a switching circuit coupled to the first voltage regulator section and to the second voltage regulator section, the switching circuit operating the first voltage regulator section and the second voltage regulator section in a normal mode, and operating only the second voltage regulator section in a power gating mode.
摘要翻译：双输出电压调节器电路包括第一电压调节器部分，第一电压调节器部分具有第一调节电压输出，耦合到第一电压调节器部分的第二电压调节器部分，具有第二调节电压输出的第二电压调节器，以及开关电路，其耦合到所述第一电压调节器部分和所述第二电压调节器部分，所述开关电路以正常模式操作所述第一电压调节器部分和所述第二电压调节器部分，并且仅在功率门控中操作所述第二电压调节器部分模式。

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