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11. 发明授权

US07376775B2 Apparatus, system, and method to enable transparent memory hot plug/remove 有权
标题翻译：装置，系统和方法，使透明内存热插拔/移除
公开(公告)号：US07376775B2
公开(公告)日：2008-05-20
申请号：US10749929
申请日：2003-12-29
申请人： Lily Pao Looi , Stanley Steven Kulick , Dean A Mulla , Ashish Gupta , Keith R. Pflederer , Shivnandan D. Kaushik , Mohan J. Kumar , James B. Crossland
发明人： Lily Pao Looi , Stanley Steven Kulick , Dean A Mulla , Ashish Gupta , Keith R. Pflederer , Shivnandan D. Kaushik , Mohan J. Kumar , James B. Crossland
IPC分类号： G06F13/00
CPC分类号： G06F11/1666 , G06F13/16
摘要： In some embodiments, an apparatus includes a processor, an expander memory bridge location, a memory coupled to the expander memory bridge location, and a bus controller including intercept logic to intercept and block communication from the processor to the expander memory bridge location and to emulate an expander memory bridge. In some embodiments, a method includes intercepting and blocking a status request to a device, regardless of whether the device is installed, and responding to the status request.
摘要翻译：在一些实施例中，一种装置包括处理器，扩展器存储器桥位置，耦合到扩展器存储器桥位置的存储器，以及总线控制器，其包括拦截和阻止从处理器到扩展器存储器桥位置的通信的截距逻辑，并且模拟一个扩展记忆桥。在一些实施例中，一种方法包括拦截和阻止对设备的状态请求，而不管该设备是否被安装，以及响应状态请求。

12. 发明授权

US06971098B2 Method and apparatus for managing transaction requests in a multi-node architecture 失效
标题翻译：用于管理多节点架构中的事务请求的方法和装置
公开(公告)号：US06971098B2
公开(公告)日：2005-11-29
申请号：US09891522
申请日：2001-06-27
申请人： Manoj Khare , Akhilesh Kumar , Ioannis Schoinas , Lily Pao Looi
发明人： Manoj Khare , Akhilesh Kumar , Ioannis Schoinas , Lily Pao Looi
IPC分类号： G06F9/46 , G06F9/54 , G06F15/163
CPC分类号： G06F9/52 , G06F12/0833
摘要： Embodiments of the present invention relate to methods and apparatus for managing transaction requests in a multi-node architecture. In one embodiment, a previously received ordered group request may be forwarded to a destination agent. Whether a next received ordered group request belongs to a same ordered group as the previously received ordered group request may be determined. Additionally, it may be determined whether an ordering fork is encountered if the next received ordered group request belongs to the same ordered group as the previously received ordered group request. If an ordering fork is encountered, it may be determined whether a request complete message for the previously received ordered group request has been received. If the request complete message for the previously received ordered group request has not been received and the next received ordered group request in the same ordered group is at least one of a un-ordered request and a forward-ordered request, then the next received ordered group request may be forwarded to the destination agent after the request complete message for the previously received at least one of a forward-ordered request and a sequential-ordered request issued on a different path at the ordering fork has been received.
摘要翻译：本发明的实施例涉及用于在多节点架构中管理事务请求的方法和装置。在一个实施例中，先前接收到的有序组请求可以被转发到目的地代理。可以确定下一个接收到的有序组请求是否属于与先前接收的有序组请求相同的有序组。此外，如果下一个接收到的有序组请求属于与先前接收的有序组请求相同的有序组，则可以确定是否遇到排序分支。如果遇到订货叉，则可以确定是否已经接收到先前接收到的订购组请求的请求完成消息。如果先前接收到的订购组请求的请求完成消息未被接收，并且相同有序组中的下一个接收到的有序组请求是未排序请求和转发请求中的至少一个，则下一个接收到的订单在已经接收到先前接收到的顺序请求和在订购叉上的不同路径上发布的顺序请求的请求的至少一个的请求完成消息之后，组请求可以被转发到目的地代理。

13. 发明授权

US06810467B1 Method and apparatus for centralized snoop filtering 有权
标题翻译：用于集中侦听过滤的方法和装置
公开(公告)号：US06810467B1
公开(公告)日：2004-10-26
申请号：US09643382
申请日：2000-08-21
申请人： Manoj Khare , Faye A. Briggs , Kai Cheng , Lily Pao Looi
发明人： Manoj Khare , Faye A. Briggs , Kai Cheng , Lily Pao Looi
IPC分类号： G06F1208
CPC分类号： G06F12/0831 , G06F12/0822 , G06F12/0828 , G06F2212/507
摘要： An example embodiment of a computer system utilizing a central snoop filter includes several nodes coupled together via a switching device. Each of the nodes may include several processors and caches as well as a block of system memory. All traffic from one node to another takes place through the switching device. The switching device includes a snoop filter that tracks cache line coherency information for all caches in the computer system. The snoop filter has enough entries to track the tags and state information for all entries in all caches in all of the system's nodes. In addition to the tag and state information, the snoop filter stores information indicating which of the nodes has a copy of each cache line. The snoop filter serves in part to keep snoop transactions from being performed at nodes that do not contain a copy of the subject cache line, thereby reducing system overhead, reducing traffic across the system interconnect busses, and reducing the amount of time required to perform snoop transactions.
摘要翻译：利用中央窥探滤波器的计算机系统的示例性实施例包括经由交换设备耦合在一起的多个节点。每个节点可以包括几个处理器和高速缓存以及系统存储器块。从一个节点到另一个节点的所有业务通过交换设备进行。交换设备包括一个窥探过滤器，其跟踪计算机系统中所有高速缓存的高速缓存行一致性信息。监听过滤器具有足够的条目来跟踪所有系统节点中所有高速缓存中所有条目的标签和状态信息。除了标签和状态信息之外，窥探过滤器存储指示哪个节点具有每个高速缓存行的副本的信息。窥探过滤器部分地用于在不包含主体高速缓存行的副本的节点处执行窥探事务，从而减少系统开销，减少跨系统互连总线的流量，并减少执行窥探所需的时间量交易。

14. 发明授权

US06195722B1 Method and apparatus for deferring transactions on a host bus having a third party agent 失效
标题翻译：用于在具有第三方代理的主机总线上推迟交易的方法和装置
公开(公告)号：US06195722B1
公开(公告)日：2001-02-27
申请号：US09013776
申请日：1998-01-26
申请人： Rajee Ram , Lily Pao Looi , Suresh S. Chittor , David R. Jackson
发明人： Rajee Ram , Lily Pao Looi , Suresh S. Chittor , David R. Jackson
IPC分类号： G06F1338
CPC分类号： G06F13/387
摘要： A method and apparatus for third party agent transaction deferral on a host bus. A host bus transaction request is received from a device, and transaction information related to the transaction request is stored in an out of order queue. An indication is received from the third party agent that the transaction has been deferred, and the stored transaction information is updated to reflect that the transaction has been deferred.
摘要翻译：一种用于在主机总线上延迟第三方代理事务的方法和装置。从设备接收主机总线事务请求，并且与事务请求相关的事务信息存储在乱序队列中。从第三方代理接收到交易被推迟的指示，并且存储的交易信息被更新以反映交易被推迟。

15. 发明授权

US6134632A Controller that supports data merging utilizing a slice addressable memory array 失效
标题翻译：支持利用片可寻址存储器阵列进行数据合并的控制器
公开(公告)号：US6134632A
公开(公告)日：2000-10-17
申请号：US013094
申请日：1998-01-26
申请人： Lily Pao Looi , Sin Tan , John Urbanski , Christopher Van Beek
发明人： Lily Pao Looi , Sin Tan , John Urbanski , Christopher Van Beek
IPC分类号： G06F12/08 , G06F12/02
CPC分类号： G06F12/0835 , G06F12/0804 , Y10S707/99942
摘要： A computer system including a slice-addressable multi-port memory array is disclosed. The slice-addressable multi-port memory array provides a mechanism for efficient data merging in a memory controller in accordance with an associated array of slice-enable bits. Each slice of the memory array is individually designated by a slice-enable bit, and only those slices of a word line enabled for writing that are designated by a slice-enable bit are modified during a write operation. In a subsequent write-merge operation, the slices of the word line enabled for writing that were not designated by slice-enable bits during the write operation are modified, and the slices that were modified during the preceding write operation are unaffected, thereby providing for efficient merger of data from the write operation and data from the write-merge operation in a single word line. Also provided is a method of preserving cache coherency in a computer system when a hit on a modified line in a cache is detected during a memory-write operation. The method includes setting a slice enable bit associated with each slice of the cache line modified by the memory write operation; writing data to slices of a word line associated with the set slice enable bits in the slice-addressable random access memory buffer; and write-merging data from the modified cache line to slices of the word line not associated with the set slice-enable bits in the slice-addressable random access memory buffer.
摘要翻译：公开了一种包括片可寻址多端口存储器阵列的计算机系统。片可寻址的多端口存储器阵列提供了一种用于根据关联的片启用位阵列在存储器控制器中有效地数据合并的机制。存储器阵列的每个片段由片启用位分别指定，并且在写操作期间仅修改由片启用位指定的能够写入的字线的那些片。在随后的写合并操作中，修改了在写操作期间未被片使能位指定的写入字线的片，并且在前一写操作期间被修改的片不受影响，从而提供来自写入操作的数据的高效合并和来自写入合并操作的数据在单个字线中。还提供了当在存储器写入操作期间检测到高速缓存中的修改的行上的命中时，在计算机系统中保持高速缓存一致性的方法。该方法包括设置与通过存储器写入操作修改的高速缓存行的每个片段相关联的限幅使能位; 将数据写入与所述片可寻址随机存取存储器缓冲器中的所述设置片使能位相关联的字线的片; 以及从所述修改的高速缓存行将所述数据写入到与所述片可寻址随机存取存储器缓冲器中的所述设置的片使能位不相关联的字线的片。

16. 发明授权

US5996038A Individually resettable bus expander bridge mechanism 失效
标题翻译：单独复位总线扩展桥机构
公开(公告)号：US5996038A
公开(公告)日：1999-11-30
申请号：US13773
申请日：1998-01-26
申请人： Lily Pao Looi , Sin Tan , James Andrew Sutton, II
发明人： Lily Pao Looi , Sin Tan , James Andrew Sutton, II
IPC分类号： G06F13/40 , G06F13/00 , G06F13/42
CPC分类号： G06F13/4045
摘要： A computer system including individually resettable bus expander bridges is described. A master bus controller provides an interface between at least one processor and at least one independently resettable bus expander bridge associated with one or more expansion buses. A bus expander bridge can be reset independently from the rest of the system when the master bus controller asserts a reset control signal that is applied to the bus expander bridge without affecting the operation of any other bus expander bridges or devices in the computer system not directly coupled to the expansion bus(es) being reset. When a reset control signal is asserted, the bus expander bridge being reset and the bus(es) associated with the bus expander bridge are reset to a default state. Once the reset process has had sufficient time for completion, the reset control signal is deasserted by the master bus controller and the bus expander bridge resumes operation.
摘要翻译：描述了包括单独可复位的总线扩展器桥的计算机系统。主总线控制器提供至少一个处理器与至少一个与一个或多个扩展总线相关联的可独立复位的总线扩展器桥接口。当主总线控制器断言施加到总线扩展器桥的复位控制信号，而不直接影响计算机系统中任何其他总线扩展器桥或器件的操作时，总线扩展器桥可以独立于系统的其余部分复位耦合到扩展总线被复位。当复位控制信号被断言时，总线扩展器桥被复位，并且与总线扩展器桥相关联的总线被复位到默认状态。一旦复位过程已经有足够的时间完成，复位控制信号被主总线控制器断开，总线扩展器桥恢复运行。

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