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11. 发明申请

US20070218621A1 Integration of strained Ge into advanced CMOS technology 有权
标题翻译：将应变锗融入先进的CMOS技术
公开(公告)号：US20070218621A1
公开(公告)日：2007-09-20
申请号：US11799261
申请日：2007-04-10
申请人： Huiling Shang , Meikei Leong , Jack Chu , Kathryn Guarini
发明人： Huiling Shang , Meikei Leong , Jack Chu , Kathryn Guarini
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L21/823807 , H01L27/1203 , H01L29/1054 , H01L29/7841
摘要： A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.
摘要翻译：公开了一种用于压缩应变Ge层中的PFET器件的结构和方法。这种器件的制造方法与标准CMOS技术兼容，并且具有完全可扩展性。该处理包括超过50％Ge含量缓冲层，纯Ge层和SiGe顶层的选择性外延沉积。承载在压缩应变Ge层中的制造掩埋沟道PMOS器件相对于类似的Si器件显示出优异的器件特性。

12. 发明授权

US06803266B2 Process for passivating the semiconductor-dielectric interface of a MOS device and MOS device formed thereby 失效
标题翻译：钝化MOS器件的半导体介质接口和由此形成的MOS器件的工艺
公开(公告)号：US06803266B2
公开(公告)日：2004-10-12
申请号：US10249184
申请日：2003-03-20
申请人： Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
发明人： Paul M. Solomon , Douglas A. Buchanan , Eduard A. Cartier , Kathryn W. Guarini , Fenton R. McFeely , Huiling Shang , John J. Yourkas
IPC分类号： H01L21336
CPC分类号： H01L29/517 , H01L21/263 , H01L21/28079 , H01L29/495 , Y10S438/91
摘要： A process for passivating the semiconductor-dielectric interface of a MOS structure to reduce the interface state density to a very low level. A particular example is a MOSFET having a tungsten electrode that in the past has prevented passivation of the underlying semiconductor-dielectric interface to an extent sufficient to reduce the interface state density to less than 5×1010/cm2−eV. Though substantially impervious to molecular hydrogen, thin tungsten layers are shown to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused through a tungsten electrode into an underlying semiconductor-dielectric interface. Three general approaches are encompassed: forming an aluminum-tungsten electrode stack in the presence of hydrogen so as to store atomic hydrogen between the tungsten and aluminum layers, followed by an anneal to cause the atomic hydrogen to diffuse through the tungsten layer and into the interface; subjecting a tungsten electrode to hydrogen plasma, during which atomic hydrogen diffuses through the electrode and into the semiconductor-dielectric interface; and implanting atomic hydrogen into tungsten electrode, followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.
摘要翻译：一种用于钝化MOS结构的半导体 - 电介质界面以将界面态密度降低到非常低的水平的方法。具体的示例是具有钨电极的MOSFET，其过去已经阻止下面的半导体 - 电介质界面的钝化达到足以将界面态密度降低到小于5×10 10 / cm 2 -eV的程度。虽然基本上不透分子氢，但是显示出薄钨层可以透过原子氢，使原子氢能够通过钨电极扩散到下面的半导体 - 电介质界面。包括三种一般方法：在氢的存在下形成铝 - 钨电极堆叠，以便在钨和铝层之间存储原子氢，随后进行退火，使原子氢扩散通过钨层并进入界面 ; 使钨电极经受氢等离子体，其中原子氢通过电极扩散并进入半导体 - 电介质界面; 并将原子氢注入钨电极中，随后进行退火，使原子氢扩散通过电极并进入半导体 - 电介质界面。

13. 发明授权

US08558313B2 Bulk substrate FET integrated on CMOS SOI 有权
标题翻译：集成在CMOS SOI上的散装衬底FET
公开(公告)号：US08558313B2
公开(公告)日：2013-10-15
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

14. 发明授权

US08154130B2 Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby 有权
标题翻译：自对准金属与Ge形成的基板和由此形成的结构形成接触
公开(公告)号：US08154130B2
公开(公告)日：2012-04-10
申请号：US12107992
申请日：2008-04-23
申请人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
发明人： Cyril Cabral, Jr. , Roy A. Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
IPC分类号： H01L29/40
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.
摘要翻译：提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。在暴露的区域中，含Ge衬底与含Si金属层接触。然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。在一些实施方案中，附加的退火步骤可以跟随去除步骤。本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

15. 发明申请

US20110318897A1 Method of Forming a Shallow Trench Isolation Embedded Polysilicon Resistor 有权
标题翻译：形成浅沟槽隔离嵌入式多晶硅电阻器的方法
公开(公告)号：US20110318897A1
公开(公告)日：2011-12-29
申请号：US12823168
申请日：2010-06-25
申请人： Huiling Shang , Ying Li , Henry K. Utomo
发明人： Huiling Shang , Ying Li , Henry K. Utomo
IPC分类号： H01L21/02
CPC分类号： H01L28/20 , H01L21/76229 , H01L27/0629
摘要： Forming a polysilicon embedded resistor within the shallow trench isolations separating the active area of two adjacent devices, minimizing the electrical interaction between two devices and reducing the capacitive coupling or leakage therebetween. The precision polysilicon resistor is formed independently from the formation of gate electrodes by creating a recess region within the STI region when the polysilicon resistor is embedded within the STI recess region. The polysilicon resistor is decoupled from the gate electrode, making it immune to gate electrode related processes. The method forms the polysilicon resistor following the formation of STIs but before the formation of the p-well and n-well implants. In another embodiment the resistor is formed following the formation of the STIs but after the formation of the well implants.
摘要翻译：在分离两个相邻器件的有源区域的浅沟槽隔离件之间形成多晶硅嵌入式电阻器，最小化两个器件之间的电气相互作用，并减少它们之间的电容耦合或泄漏。当多晶硅电阻器嵌入STI凹陷区域内时，通过在STI区域内形成凹陷区域，独立于形成栅电极而形成精密多晶硅电阻器。多晶硅电阻器与栅极电极分离，使其免受与栅电极相关的工艺的影响。该方法在形成STI之后但在形成p阱和n阱注入之前形成多晶硅电阻器。在另一个实施例中，在形成STI之后但在形成井注入之后形成电阻器。

16. 发明授权

US08592264B2 Source-drain extension formation in replacement metal gate transistor device 有权
标题翻译：源极 - 漏极扩展形成在替代金属栅极晶体管器件中
公开(公告)号：US08592264B2
公开(公告)日：2013-11-26
申请号：US13332991
申请日：2011-12-21
申请人： Takashi Ando , Huiming Bu , Ramachandra Divakaruni , Bruce B. Doris , Chung-Hsun Lin , Huiling Shang , Tenko Yamashita
发明人： Takashi Ando , Huiming Bu , Ramachandra Divakaruni , Bruce B. Doris , Chung-Hsun Lin , Huiling Shang , Tenko Yamashita
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/2658 , H01L21/26586 , H01L21/268 , H01L29/42384 , H01L29/4908 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/6653 , H01L29/66537 , H01L29/66545 , H01L29/6656 , H01L29/6659 , H01L29/78621
摘要： A method includes forming on a surface of a semiconductor a dummy gate structure comprised of a plug; forming a first spacer surrounding the plug, the first spacer being a sacrificial spacer; and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form a source extension region and a drain extension region, where the implanted dopant species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source extension and the drain extension implant. The method further includes forming a second spacer surrounding the first spacer, removing the first spacer and the plug to form an opening, and depositing a gate stack in the opening.
摘要翻译：一种方法包括在半导体的表面上形成由插头构成的虚拟栅极结构; 形成围绕所述插塞的第一间隔件，所述第一间隔件是牺牲间隔件; 以及执行成角度的离子注入，以便将掺杂剂物质注入与所述第一间隔物的外侧壁相邻的所述半导体的表面中，以形成源延伸区域和漏极延伸区域，其中所述注入的掺杂剂物质在所述外侧壁的第一间隔物的量是离子注入的角度的函数。该方法还包括执行激光退火以激活源延伸和漏极延伸植入。该方法还包括形成围绕第一间隔件的第二间隔件，去除第一间隔件和插塞以形成开口，以及在开口中沉积栅极堆叠。

17. 发明申请

US20110163383A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20110163383A1
公开(公告)日：2011-07-07
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

18. 发明申请

US20050250301A1 Self-aligned metal to form contacts to Ge containing substrates and structure formed thereby 有权
标题翻译：自对准金属与Ge形成的基板和由此形成的结构形成接触
公开(公告)号：US20050250301A1
公开(公告)日：2005-11-10
申请号：US10838378
申请日：2004-05-04
申请人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
发明人： Cyril Cabral , Roy Carruthers , Christophe Detavernier , Simon Gaudet , Christian Lavoie , Huiling Shang
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336
CPC分类号： H01L21/28525 , H01L21/28052 , H01L21/28518 , H01L29/665
摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.
摘要翻译：提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。在暴露的区域中，含Ge衬底与含Si金属层接触。然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。在一些实施方案中，附加的退火步骤可以跟随去除步骤。本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

19. 发明授权

US08232599B2 Bulk substrate FET integrated on CMOS SOI 有权
标题翻译：集成在CMOS SOI上的散装衬底FET
公开(公告)号：US08232599B2
公开(公告)日：2012-07-31
申请号：US12683456
申请日：2010-01-07
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/12 , H01L21/86
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

20. 发明申请

US20120187492A1 BULK SUBSTRATE FET INTEGRATED ON CMOS SOI 有权
标题翻译：集成在CMOS SOI上的基极FET
公开(公告)号：US20120187492A1
公开(公告)日：2012-07-26
申请号：US13425681
申请日：2012-03-21
申请人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
发明人： Anthony I. Chou , Arvind Kumar , Shreesh Narasimha , Ning Su , Huiling Shang
IPC分类号： H01L27/088
CPC分类号： H01L27/1207 , H01L21/84
摘要： An integrated circuit is provided that integrates an bulk FET and an SOI FET on the same chip, where the bulk FET includes a gate conductor over a gate oxide formed over a bulk substrate, where the gate dielectric of the bulk FET has the same thickness and is substantially coplanar with the buried insulating layer of the SOI FET. In a preferred embodiment, the bulk FET is formed from an SOI wafer by forming bulk contact trenches through the SOI layer and the buried insulating layer of the SOI wafer adjacent an active region of the SOI layer in a designated bulk device region. The active region of the SOI layer adjacent the bulk contact trenches forms the gate conductor of the bulk FET which overlies a portion of the underlying buried insulating layer, which forms the gate dielectric of the bulk FET.
摘要翻译：提供了一种集成电路，其将同一芯片上的体FET和SOI FET集成在一起，其中，本体FET包括在大块衬底上形成的栅极氧化物上的栅极导体，其中本体FET的栅极电介质具有相同的厚度，与SOI FET的掩埋绝缘层基本共面。在优选实施例中，通过在指定的大容量器件区域中与SOI层的有源区相邻的SOI层和SOI晶片的掩埋绝缘层形成体接触沟槽，从SOI晶片形成本体FET。邻近体接触沟槽的SOI层的有源区域形成体FET的栅极导体，其覆盖形成本体FET的栅极电介质的下层掩埋绝缘层的一部分。

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