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11. 发明授权

US06442720B1 Technique to decrease the exposure time of infrared imaging of semiconductor chips for failure analysis 失效
标题翻译：降低半导体芯片红外成像曝光时间的技术进行故障分析
公开(公告)号：US06442720B1
公开(公告)日：2002-08-27
申请号：US09326226
申请日：1999-06-04
申请人： Timothy J. Koprowski , Mary P. Kusko , Richard F. Rizzolo , Peilin Song
发明人： Timothy J. Koprowski , Mary P. Kusko , Richard F. Rizzolo , Peilin Song
IPC分类号： G01R3128
CPC分类号： G01R31/31858
摘要： The present invention can include a method and system for testing IC chips, including the steps of performing a binary search to a first failing pattern, determining a failing sink latch, performing a back cone trace to determine all source latches, determining source latch logic states, positioning the source latch logic states in a scan chain, exercising a chip scan path by applying logic transitions on the source latches in the absence of a system L1 clock, and observing an exercised failing circuit. The invention can include the use of PICA techniques to observe the exercised failing circuit. In another embodiment, the invention can include using LBIST or a WRP technique to search for the failing pattern. In yet another it includes the step of using an algorithm to exercise the exercised failing circuit. In another embodiment, the method includes the step of creating a net pattern to be scanned including a sum of an original pattern causing a failing circuit to be exercised, and one or more shifted versions of the original pattern. The algorithm can include a step where one of the shifted versions is shifted a number of clocks wherein the number of clocks is equal to the length of the original pattern. In one embodiment, one of the shifted versions is shifted a number of clocks, wherein the number of clocks is chosen so that the sum of the original pattern and the one of the shifted versions does not cause a scan conflict. In another embodiment the method further includes the step of using an algorithm to densify the pattern set.
摘要翻译：本发明可以包括用于测试IC芯片的方法和系统，包括以下步骤：对第一故障模式执行二进制搜索，确定故障接收器锁存器，执行后锥迹线以确定所有源锁存器，确定源锁存器逻辑状态将源锁存器逻辑状态定位在扫描链中，通过在没有系统L1时钟的情况下在源锁存器上施加逻辑转换并观察行使的故障电路来执行芯片扫描路径。本发明可以包括使用PICA技术来观察行使的故障电路。在另一个实施例中，本发明可以包括使用LBIST或WRP技术来搜索失败的模式。在另一方面，它包括使用算法来锻炼锻炼的故障电路的步骤。在另一个实施例中，该方法包括创建要被扫描的网络图案的步骤，包括导致执行故障电路的原始图案的和以及原始图案的一个或多个偏移版本。该算法可以包括一个步骤，其中移位版本中的一个被移位了多个时钟，其中时钟数等于原始图案的长度。在一个实施例中，移位版本中的一个被移位了多个时钟，其中选择时钟的数量，使得原始模式和移位版本之一的总和不会引起扫描冲突。在另一个实施例中，该方法还包括使用算法来密集模式集的步骤。

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