专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07768017B2 Silicon carbide semiconductor device and manufacturing method therefor 失效
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US07768017B2
公开(公告)日：2010-08-03
申请号：US10581247
申请日：2004-12-01
申请人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.
摘要翻译：为了防止由于使用碳化硅半导体的双极性半导体器件随时间的变化引起的正向电压的增加，缓冲层，漂移层和其他p型和n型半导体层形成在生长表面，其由具有偏角角度的硅碳化物半导体的晶体的表面给出; （000-1）碳表面8度，以每小时薄膜增加率为10μm/小时的膜生长速率，比常规对应物高3倍以上。硅烷和丙烷材料气体和掺杂气体的流速大大增加，以提高膜生长速率。

12. 发明申请

US20090317983A1 Process for Producing Silicon Carbide Semiconductor Device 失效
标题翻译：生产碳化硅半导体器件的工艺
公开(公告)号：US20090317983A1
公开(公告)日：2009-12-24
申请号：US12067028
申请日：2006-09-01
申请人： Toshiyuki Miyanagi , Hidekazu Tsuchida , Isaho Kamata , Masahiro Nagano , Yoshitaka Sugawara , Koji Nakayama , Ryosuke Ishii
发明人： Toshiyuki Miyanagi , Hidekazu Tsuchida , Isaho Kamata , Masahiro Nagano , Yoshitaka Sugawara , Koji Nakayama , Ryosuke Ishii
IPC分类号： H01L21/26
CPC分类号： H01L29/66068 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/0485 , H01L29/1608 , H01L29/861
摘要： In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.
摘要翻译：在从碳化硅单晶衬底的表面生长的碳化硅外延膜内的电流通过期间电子和空穴彼此复合的双极性碳化硅半导体器件中，本文所述的目的是减少通过电流通过而扩展的堆垛层错的核，由此抑制双极性碳化硅半导体器件的正向电压的增加。在制造双极性碳化硅半导体器件的方法中，在最后的制造工序中，在300℃以上的温度下进行热处理。优选地，上述热处理在电极形成之后进行，然后将所得到的双极性碳化硅半导体器件安装在封装中。

13. 发明申请

US20070290211A1 Bipolar Semiconductor Device and Process for Producing the Same 审中-公开
标题翻译：双极半导体器件及其制造方法
公开(公告)号：US20070290211A1
公开(公告)日：2007-12-20
申请号：US10594045
申请日：2005-03-25
申请人： Koji Nakayama , Yoshitaka Sugawara , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L21/20 , H01L21/205 , H01L21/302 , H01L21/331 , H01L21/336 , H01L29/73 , H01L29/78 , H01L29/861
CPC分类号： H01L29/8613 , H01L21/02019 , H01L21/02024 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/0262 , H01L21/02661
摘要： A process for manufacturing a bipolar type semiconductor device in which at least a part of a region where an electron and a hole are recombined during current flowing is formed with a silicon carbide epitaxial layer that has been grown from the surface of a silicon carbide substrate, is characterized by that the surface of the silicon carbide substrate is treated by hydrogen etching and the epitaxial layer is then formed by the epitaxial growth of silicon carbide from the treated surface. A propagation of a basal plane dislocation to the epitaxial layer can be further reduced by treating the surface of the silicon carbide substrate by using chemical mechanical polishing and hydrogen etching in this order.
摘要翻译：一种用于制造双极型半导体器件的方法，其中在电流流动期间电子和空穴复合的区域的至少一部分由从碳化硅衬底的表面生长的碳化硅外延层形成，其特征在于，通过氢蚀刻处理碳化硅衬底的表面，然后通过从处理过的表面外延生长碳化硅形成外延层。通过使用化学机械抛光和氢蚀刻依次处理碳化硅衬底的表面，可以进一步减少基面平面位错到外延层的传播。

14. 发明申请

US20070090370A1 Silicon carbide semiconductor device and manufacturing method therefor 失效
标题翻译：碳化硅半导体器件及其制造方法
公开(公告)号：US20070090370A1
公开(公告)日：2007-04-26
申请号：US10581247
申请日：2004-12-01
申请人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L31/0312
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.
摘要翻译：为了防止由于使用碳化硅半导体的双极性半导体器件随时间的变化引起的正向电压的增加，缓冲层，漂移层和其他p型和n型半导体层形成在生长表面，其具有距离晶体的（000-1）碳表面具有8度偏离角度的碳化硅半导体的晶体表面，膜厚度为膜厚度每小时h的增加速率为10mum / h，是传统方式的三倍或更高。硅烷和丙烷材料气体和掺杂气体的流速大大增加，以提高膜生长速率。

15. 发明授权

US08367510B2 Process for producing silicon carbide semiconductor device 失效
标题翻译：碳化硅半导体器件的制造方法
公开(公告)号：US08367510B2
公开(公告)日：2013-02-05
申请号：US12067028
申请日：2006-09-01
申请人： Toshiyuki Miyanagi , Hidekazu Tsuchida , Isaho Kamata , Masahiro Nagano , Yoshitaka Sugawara , Koji Nakayama , Ryosuke Ishii
发明人： Toshiyuki Miyanagi , Hidekazu Tsuchida , Isaho Kamata , Masahiro Nagano , Yoshitaka Sugawara , Koji Nakayama , Ryosuke Ishii
IPC分类号： H01L21/331
CPC分类号： H01L29/66068 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02576 , H01L21/02579 , H01L21/0262 , H01L21/0485 , H01L29/1608 , H01L29/861
摘要： In a bipolar silicon carbide semiconductor device in which an electron and a hole recombine with each other during current passage within a silicon carbide epitaxial film grown from a surface of a silicon carbide single crystal substrate, an object described herein is the reduction of defects which are the nuclei of a stacking fault which is expanded by current passage, thereby suppressing the increase of the forward voltage of the bipolar silicon carbide semiconductor device. In a method for producing a bipolar silicon carbide semiconductor device, the device is subjected to a thermal treatment at a temperature of 300° C. or higher in the final step of production. Preferably, the above-mentioned thermal treatment is carried out after the formation of electrodes and then the resulting bipolar silicon carbide semiconductor device is mounted in a package.
摘要翻译：在从碳化硅单晶衬底的表面生长的碳化硅外延膜内的电流通过期间电子和空穴彼此复合的双极性碳化硅半导体器件中，本文所述的目的是减少通过电流通过而扩展的堆垛层错的核，由此抑制双极性碳化硅半导体器件的正向电压的增加。在制造双极性碳化硅半导体器件的方法中，在最后的制造工序中，在300℃以上的温度下进行热处理。优选地，上述热处理在电极形成之后进行，然后将所得到的双极性碳化硅半导体器件安装在封装中。

16. 发明授权

US07960738B2 Silicon carbide semiconductor device and manufacturing method therefor 失效
公开(公告)号：US07960738B2
公开(公告)日：2011-06-14
申请号：US12801681
申请日：2010-06-21
申请人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

17. 发明申请

US20100258817A1 Silicon carbide semiconductor device and manufacturing method therefor 失效
公开(公告)号：US20100258817A1
公开(公告)日：2010-10-14
申请号：US12801681
申请日：2010-06-21
申请人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
发明人： Koji Nakayama , Yoshitaka Sugawara , Katsunori Asano , Hidekazu Tsuchida , Isaho Kamata , Toshiyuki Miyanagi , Tomonori Nakamura
IPC分类号： H01L29/24
CPC分类号： H01L29/868 , H01L29/045 , H01L29/0619 , H01L29/1608 , H01L29/66068 , H01L29/73 , H01L29/7397
摘要： With a view to preventing increases in forward voltage due to a change with the lapse of time of a bipolar semiconductor device using a silicon carbide semiconductor, a buffer layer, a drift layer and other p-type and n-type semiconductor layers are formed on a growth surface, which is given by a surface of a crystal of a silicon carbide semiconductor having an off-angle θ of 8 degrees from a (000-1) carbon surface of the crystal, at a film growth rate having a film-thickness increasing rate per hour h of 10 μm/h, which is three times or more higher than conventional counterparts. The flow rate of silane and propane material gases and dopant gases is largely increased to enhance the film growth rate.

18. 发明申请

US20050181627A1 Method for preparing sic crystal and sic crystal 有权
标题翻译：制备晶体和晶体晶体的方法
公开(公告)号：US20050181627A1
公开(公告)日：2005-08-18
申请号：US10508130
申请日：2003-03-19
申请人： Isaho Kamata , Hidekazu Tsuchida
发明人： Isaho Kamata , Hidekazu Tsuchida
IPC分类号： C30B25/02 , H01L21/31
CPC分类号： C30B25/02 , C30B29/36
摘要： A process for closing hollow-core defects, called micropipes, during growth by CVD of a SiC crystal on a SiC single crystal substrate having hollow-core defects, and a crystal obtained according to the process, by contacting the SiC crystal with a source gas adjusted to a C/Si atom ratio range in which the crystal growth rate is determined by the carbon atom supply limitation, then epitaxially growing and laminating a plurality of SiC crystal layers, wherein hollow-core defects in the SiC single crystal substrate dissociate into a plurality of dislocations given by small Burgers vector in order not to propagate to the crystal surface. In addition, the present invention provides a fabrication process of a SiC crystal, wherein a first SiC crystal is made as a buffer layer, and a further SiC crystal is layered thereon using a source gas adjusted to be higher than that of the C/Si ratio when forming the buffer layer, whereby a desired film property is conferred.
摘要翻译：在具有中空芯缺陷的SiC单晶衬底上的SiC晶体的CVD生长期间闭合中空缺陷的方法，以及根据该工艺获得的晶体，通过使SiC晶体与源气体调整为通过碳原子供给限制来确定晶体生长速率的C / Si原子比范围，然后外延生长并层叠多个SiC晶体层，其中SiC单晶衬底中的中空缺陷解离成为了不传播到晶体表面，由小汉堡矢量给出多个位错。另外，本发明提供一种SiC晶体的制造方法，其中使用第一SiC晶体作为缓冲层，并且使用调节为高于C / Si的源气体将另外的SiC晶体层叠在其上形成缓冲层的比例，由此赋予所需的膜性质。

19. 发明授权

US08716718B2 Epitaxial SiC single crystal substrate and method of manufacture of epitaxial SiC single crystal substrate 有权
标题翻译：外延SiC单晶衬底及外延SiC单晶衬底的制造方法
公开(公告)号：US08716718B2
公开(公告)日：2014-05-06
申请号：US13617596
申请日：2012-09-14
申请人： Kenji Momose , Michiya Odawara , Keiichi Matsuzawa , Hajime Okumura , Kazutoshi Kojima , Yuuki Ishida , Hidekazu Tsuchida , Isaho Kamata
发明人： Kenji Momose , Michiya Odawara , Keiichi Matsuzawa , Hajime Okumura , Kazutoshi Kojima , Yuuki Ishida , Hidekazu Tsuchida , Isaho Kamata
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： C23C16/46 , C23C16/325 , C30B25/02 , C30B29/36 , H01L21/02378 , H01L21/02433 , H01L21/02529 , H01L21/02576 , H01L21/0262
摘要： An epitaxial SiC single crystal substrate including a SiC single crystal wafer whose main surface is a c-plane or a surface that inclines a c-plane with an angle of inclination that is more than 0 degree but less than 10 degrees, and SiC epitaxial film that is formed on the main surface of the SiC single crystal wafer, wherein the dislocation array density of threading edge dislocation arrays that are formed in the SiC epitaxial film is 10 arrays/cm2 or less.
摘要翻译：外延SiC单晶衬底，其包括主表面为c面的SiC单晶晶片或倾斜角度大于0度但小于10度的c面倾斜的表面;以及SiC外延膜其形成在SiC单晶晶片的主表面上，其中形成在SiC外延膜中的穿线边缘位错阵列的位错阵列密度为10阵列/ cm 2以下。

20. 发明授权

US08154026B2 Silicon carbide bipolar semiconductor device 失效
标题翻译：碳化硅双极半导体器件
公开(公告)号：US08154026B2
公开(公告)日：2012-04-10
申请号：US12097019
申请日：2006-12-13
申请人： Ryosuke Ishii , Koji Nakayama , Yoshitaka Sugawara , Toshiyuki Miyanagi , Hidekazu Tsuchida , Isaho Kamata , Tomonori Nakamura
发明人： Ryosuke Ishii , Koji Nakayama , Yoshitaka Sugawara , Toshiyuki Miyanagi , Hidekazu Tsuchida , Isaho Kamata , Tomonori Nakamura
IPC分类号： H01L29/15
CPC分类号： H01L29/1604 , H01L21/0465 , H01L21/047 , H01L29/0615 , H01L29/0619 , H01L29/0661 , H01L29/1608 , H01L29/6606 , H01L29/66068 , H01L29/8613
摘要： In a SiC bipolar semiconductor device with a mesa structure having a SiC drift layer of a first conductive type and a SiC carrier injection layer of a second conductive type that are SiC epitaxial layers grown from a surface of a SiC single crystal substrate, the formation of stacking faults and the expansion of the area thereof are prevented and thereby the increase in forward voltage is prevented. Further, a characteristic of withstand voltage in a reverse biasing is improved. An forward-operation degradation preventing layer is formed on a mesa wall or on a mesa wall and a mesa periphery to separate spatially the surface of the mesa wall from a pn-junction interface. In one embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide low resistance layer of a second conductive type that is equipotential during the application of a reverse voltage. In another embodiment, the forward-operation degradation preventing layer is composed of a silicon carbide conductive layer of a second conductive type, and a metal layer that is equipotential during the application of a reverse voltage is formed on a surface of the silicon carbide conductive layer. In still another embodiment, the forward-operation degradation preventing layer is composed of a high resistance amorphous layer.
摘要翻译：在具有由SiC单晶衬底的表面生长的SiC外延层的具有第一导电类型的SiC漂移层和第二导电类型的SiC载流子注入层的台阶结构的SiC双极型半导体器件中，形成防止堆垛层错及其面积的膨胀，从而防止正向电压的增加。此外，提高了反向偏置中的耐受电压的特性。在台面壁或台面壁和台面周边上形成正向操作降解防止层，以在空间上分离台面壁的表面与pn结界面。在一个实施例中，正向操作降解防止层由在施加反向电压期间具有等电位的第二导电类型的碳化硅低电阻层构成。在另一个实施方案中，正向操作降解防止层由第二导电类型的碳化硅导电层构成，并且在施加反向电压期间具有等电位的金属层形成在碳化硅导电层的表面上。在另一个实施方案中，正向操作降解防止层由高电阻非晶层组成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式