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11. 发明申请

US20080062734A1 Interchangeable connection arrays for double-sided DIMM placement 有权
标题翻译：可互换连接阵列，用于双面DIMM放置
公开(公告)号：US20080062734A1
公开(公告)日：2008-03-13
申请号：US11899497
申请日：2007-09-05
申请人： Michael Leddige , Kuljit Bains , John Sprietsma
发明人： Michael Leddige , Kuljit Bains , John Sprietsma
IPC分类号： G11C5/02
CPC分类号： H01L23/49816 , G11C5/02 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H05K1/181 , H05K2201/10159 , H05K2201/10734 , H05K2203/1572 , Y02P70/611
摘要： A memory module has an array of connections. The array of connections is arranged in rows and columns such that there are first and second outer columns. Connections in the first and second outer columns can be interchanged to optimize double-side module placement on a substrate.
摘要翻译：存储器模块具有连接阵列。连接阵列以行和列排列，使得存在第一和第二外部列。可以互换第一和第二外柱中的连接，以优化在基板上的双面模块放置。

12. 发明申请

US20070220401A1 Systems, methods, and apparatuses for using the same memory type to support an error check mode and a non-error check mode 失效
标题翻译：使用相同存储器类型来支持错误检查模式和非错误检查模式的系统，方法和装置
公开(公告)号：US20070220401A1
公开(公告)日：2007-09-20
申请号：US11364107
申请日：2006-02-27
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G11C29/00
CPC分类号： G11C7/1045 , G06F11/1044 , G11C7/1006 , G11C29/42 , G11C29/52 , G11C2207/104
摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for using the same memory type in an error check mode and a non-error check mode. In some embodiments, a memory device includes at least one split bank pair of memory banks. If the memory device is in an error check mode, then, in some embodiments, data is stored in one of memory banks of the split bank pair and the corresponding error check bits are stored in the other memory bank of the split bank pair. A register bit on the memory device indicates whether it is in the error check mode or the non-error check mode. Other embodiments are described and claimed.
摘要翻译：本发明的实施例一般涉及在错误检查模式和非错误检查模式中使用相同存储器类型的系统，方法和装置。在一些实施例中，存储器设备包括至少一个分离组对的存储体。如果存储器件处于错误检查模式，则在一些实施例中，数据被存储在分离组对的存储体之一中，并且相应的错误校验位存储在分离存储体对的另一个存储体中。存储设备上的寄存器位指示是处于错误检查模式还是非错误检查模式。描述和要求保护其他实施例。

13. 发明申请

US20060117129A1 High speed DRAM cache architecture 有权
公开(公告)号：US20060117129A1
公开(公告)日：2006-06-01
申请号：US11329994
申请日：2006-01-10
申请人： Kuljit Bains , Herbert Hum , John Halbert
发明人： Kuljit Bains , Herbert Hum , John Halbert
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0864 , G06F12/0882
摘要： A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.

14. 发明申请

US20050146974A1 Method and apparatus for multiple row caches per bank 失效
标题翻译：每行多行缓存的方法和装置
公开(公告)号：US20050146974A1
公开(公告)日：2005-07-07
申请号：US10749690
申请日：2003-12-30
申请人： John Halbert , Robert Ellis , Kuljit Bains , Chris Freeman
发明人： John Halbert , Robert Ellis , Kuljit Bains , Chris Freeman
IPC分类号： G06F12/08 , G11C7/10 , G11C7/12 , G11C11/4094 , G11C8/00
CPC分类号： G11C11/4094 , G06F12/0893 , G06F2212/3042 , G11C7/065 , G11C7/1006 , G11C7/12 , G11C2207/005 , Y02D10/13
摘要： Provision and use of sets of isolators to enable the caching of the contents of at least one row of memory cells within a subarray of a bank of a memory device by a row of sense amplifiers associated with the subarray to enable faster access to write the data directed to at least one row through a write operation causing the data to written to the row of sense amplifiers versus from the row of memory cells, directly, and to store an indication that the data cached by the row of sense amplifiers is dirty.
摘要翻译：提供和使用隔离器组，以使得能够通过与子阵列相关联的一行读出放大器将存储器件组的子阵列内的至少一行存储器单元的内容缓存以使得能够更快地访问写入数据通过写入操作指向至少一行，使得数据直接从存储单元行写入读出放大器行，并存储由读出放大器行缓冲的数据变脏的指示。

15. 发明申请

US20050108469A1 Buffered memory module with implicit to explicit memory command expansion 有权
标题翻译：缓冲内存模块，具有隐式显式内存命令扩展
公开(公告)号：US20050108469A1
公开(公告)日：2005-05-19
申请号：US10713784
申请日：2003-11-13
申请人： Chris Freeman , Pete Vogt , Kuljit Bains , Robert Ellis , John Halbert , Michael Williams
发明人： Chris Freeman , Pete Vogt , Kuljit Bains , Robert Ellis , John Halbert , Michael Williams
IPC分类号： G06F13/16 , G06F12/00
CPC分类号： G06F13/16
摘要： Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, the memory module has a buffer that receives memory commands and data, and then presents those commands and data to physical memory devices through a separate interface. The buffer has the capability to accept an implicit memory command, i.e., a command that does not contain a fully-formed memory device command, but instead instructs the memory module buffer to form one or more fully-formed memory device commands to perform memory operations. Substantial memory channel bandwidth can be saved, for instance, with a command that instructs a memory module to clear a region of memory or copy a region to a second area in memory. Other embodiments are described and claimed.
摘要翻译：在实施例中包括用于缓冲存储器模块的方法和装置。在示例性系统中，存储器模块具有接收存储器命令和数据的缓冲器，然后通过单独的接口将这些命令和数据呈现给物理存储器设备。缓冲器具有接受隐含存储器命令的功能，即，不包含完全形成的存储器件命令的命令，而是指示存储器模块缓冲器形成一个或多个完全形成的存储器件命令以执行存储器操作。例如，可以通过指令存储器模块清除存储器区域或将区域复制到存储器中的第二区域的命令来保存实质存储器通道带宽。描述和要求保护其他实施例。

16. 发明授权

US5940848A Computer system and method for efficiently controlling the opening and closing of pages for an aborted row on page miss cycle 失效
标题翻译：计算机系统和方法，用于有效地控制中止的行或页错失周期的页面的打开和关闭
公开(公告)号：US5940848A
公开(公告)日：1999-08-17
申请号：US783018
申请日：1997-01-14
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00 , G11C11/407
CPC分类号： G06F12/0215 , G06F12/0897
摘要： A computer system including a processor and a storage device and a method for accessing at least one page of the storage device, are described. The computer system further includes a control circuit coupled to the processor and to the memory device. The control circuit is configured to change a state, such as open or closed, of the at least one page, when one of a page miss and row miss cycle to that at least one page is aborted. The control circuit is configured to restore the state of the at least one page a predetermined number of cycles after the state of the at least one page was changed. Performance benefits may be obtained in a computer system including a second level (L2) cache if upon a page miss or row miss cycle that has been aborted, the state of a page previously accessed is restored. The paging process efficiently controls the opening and closing of pages and takes into account the system architecture and the occurrence of certain events such as a host bus being idle, a cycle being aborted, etc.
摘要翻译：描述了包括处理器和存储设备的计算机系统以及用于访问存储设备的至少一个页面的方法。计算机系统还包括耦合到处理器和存储器件的控制电路。当所述至少一个页面的页面未命中和行错过周期中的一个中止时，所述控制电路被配置为改变所述至少一个页面的状态，诸如打开或关闭的状态。控制电路被配置为在至少一个页面的状态被改变之后将至少一个页面的状态恢复预定数量的周期。在包括第二级（L2）高速缓存的计算机系统中可以获得性能优点，如果在中止了页错失或行错过周期时，恢复了先前访问的页的状态。寻呼过程有效地控制页面的打开和关闭，并考虑到系统架构和某些事件的发生，例如主机总线空闲，中断周期等。

17. 发明申请

US20130346684A1 METHOD, APPARATUS AND SYSTEM FOR A PER-DRAM ADDRESSABILITY MODE 审中-公开
标题翻译：方法，设备和系统，用于存储器可寻址模式
公开(公告)号：US20130346684A1
公开(公告)日：2013-12-26
申请号：US13531368
申请日：2012-06-22
申请人： Kuljit Bains
发明人： Kuljit Bains
IPC分类号： G06F12/00
CPC分类号： G11C7/1045 , G11C7/109 , G11C11/4096
摘要： Techniques and mechanisms for programming an operation mode of a dynamic random access memory (DRAM) device. In an embodiment, a memory controller stores a value in a mode register of a DRAM device, the value specifying whether a per-DRAM addressability (PDA) mode of the DRAM device is enabled. An external contact of the DRAM device is coupled to the memory controller device via a signal line of a data bus. In another embodiment, the memory controller sends a signal to the external contact while the PDA mode of the DRAM device is enabled, the signal to specify whether one or more features of the DRAM device are programmable.
摘要翻译：用于编程动态随机存取存储器（DRAM）设备的操作模式的技术和机制。在一个实施例中，存储器控制器将值存储在DRAM器件的模式寄存器中，该值指定DRAM器件的每DRAM可寻址（PDA）模式是否被使能。 DRAM器件的外部触点经由数据总线的信号线耦合到存储器控制器装置。在另一个实施例中，存储器控制器在DRAM器件的PDA模式被使能的同时向外部触点发送信号，该信号指定DRAM器件的一个或多个特征是否可编程。

18. 发明授权

US07404055B2 Memory transfer with early access to critical portion 有权
标题翻译：具有早期访问关键部分的内存传输
公开(公告)号：US07404055B2
公开(公告)日：2008-07-22
申请号：US11392471
申请日：2006-03-28
申请人： Kuljit Bains , John Halbert , Greg Lemos , Randy Osborne
发明人： Kuljit Bains , John Halbert , Greg Lemos , Randy Osborne
IPC分类号： G06F12/00
CPC分类号： G06F13/1678
摘要： In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器具有第二宽度的第二格式，其中临界部分包括在第一帧中。关键部分可以包括在存储器设备等级上映射的高速缓存线。描述和要求保护其他实施例。

19. 发明申请

US20070130374A1 Multiported memory with configurable ports 审中-公开
标题翻译：具有可配置端口的多端口存储器
公开(公告)号：US20070130374A1
公开(公告)日：2007-06-07
申请号：US11280837
申请日：2005-11-15
申请人： Kuljit Bains , John Halbert , Randy Osborne
发明人： Kuljit Bains , John Halbert , Randy Osborne
IPC分类号： G06F3/00
CPC分类号： G06F13/1694
摘要： In some embodiments, a chip includes memory banks and data ports, including at least first and second data ports, coupled to the memory banks. The chip also includes control circuitry to control a configuration of the first data port to be in one of multiple configurations in response to a configuration command, wherein the available configurations for the first data port include at least two of the following: whether the first data port (1) may only be used for read transactions, (2) may only be used for write transactions, or (3) may be used for either read or write transactions while in the configuration. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括耦合到存储体的存储器组和数据端口，包括至少第一和第二数据端口。该芯片还包括控制电路，用于响应于配置命令将第一数据端口的配置控制为多个配置之一，其中第一数据端口的可用配置包括以下中的至少两个：第一数据端口（1）只能用于读取事务，（2）只能用于写入事务，或者（3）可以在配置中用于读取或写入事务。描述其他实施例。

20. 发明申请

US20060239095A1 Memory device communication using system memory bus 有权
标题翻译：使用系统内存总线的内存设备通讯
公开(公告)号：US20060239095A1
公开(公告)日：2006-10-26
申请号：US11093705
申请日：2005-03-30
申请人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas Skelton , Bill Nale
发明人： Jun Shi , Sandeep Jain , Animesh Mishra , Kuljit Bains , David Wyatt , Thomas Skelton , Bill Nale
IPC分类号： G11C7/00
CPC分类号： G11C7/04 , G11C7/1045 , G11C11/4076
摘要： Data regarding physical parameters and security and commands to send such data can be communicated between a memory device and a memory controller using a memory bus connected between the two. In one embodiment, the invention includes receiving a first command at a memory device on a memory bus, the first command being other than a read or write command, and receiving a second command together with the first command, the second command to be initiated using lines that are not used by the first command.
摘要翻译：关于物理参数和安全性的数据以及发送这样的数据的命令可以使用连接在两者之间的存储器总线在存储器件和存储器控制器之间传送。在一个实施例中，本发明包括在存储器总线上的存储器件处接收第一命令，第一命令不同于读取或写入命令，并且与第一命令一起接收第二命令，使用第一个命令未使用的行。

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