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11. 发明申请

US20070114570A1 POWER SEMICONDUCTOR DEVICE 有权
标题翻译：功率半导体器件
公开(公告)号：US20070114570A1
公开(公告)日：2007-05-24
申请号：US11626141
申请日：2007-01-23
申请人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
发明人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
IPC分类号： H01L31/00
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译：功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。在虚拟电池中设置第二导电类型的缓冲层。栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。

12. 发明申请

US20060006409A1 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US20060006409A1
公开(公告)日：2006-01-12
申请号：US11221702
申请日：2005-09-09
申请人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
发明人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
IPC分类号： H01L29/423
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译：功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。在虚拟电池中设置第二导电类型的缓冲层。栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。

13. 发明授权

US07078740B2 Power semiconductor device 有权
公开(公告)号：US07078740B2
公开(公告)日：2006-07-18
申请号：US10843571
申请日：2004-05-12
申请人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
发明人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
IPC分类号： H01L29/74 , H01L31/111
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

14. 发明授权

US07170106B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07170106B2
公开(公告)日：2007-01-30
申请号：US11221702
申请日：2005-09-09
申请人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
发明人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
IPC分类号： H01L29/74 , H01L29/423 , H01L31/111
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译：功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。在虚拟电池中设置第二导电类型的缓冲层。栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。

15. 发明授权

US06809349B2 Power semiconductor device 有权
公开(公告)号：US06809349B2
公开(公告)日：2004-10-26
申请号：US10354048
申请日：2003-01-30
申请人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
发明人： Masakazu Yamaguchi , Hideaki Ninomiya , Ichiro Omura , Tomoki Inoue
IPC分类号： H01L2974
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.

16. 发明申请

US20060237786A1 Power semiconductor device 审中-公开
标题翻译：功率半导体器件
公开(公告)号：US20060237786A1
公开(公告)日：2006-10-26
申请号：US11384260
申请日：2006-03-21
申请人： Hideaki Ninomiya , Masanobu Tsuchitani , Satoshi Teramae , Masakazu Yamaguchi , Koichi Sugiyama , Satoshi Urano , Keiko Kawamura
发明人： Hideaki Ninomiya , Masanobu Tsuchitani , Satoshi Teramae , Masakazu Yamaguchi , Koichi Sugiyama , Satoshi Urano , Keiko Kawamura
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0623 , H01L29/0653 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/7393
摘要： A power semiconductor device according to the present invention comprises: a first conductive type base layer; a second conductive type base layer selectively formed on the first conductive type base layer; an insulation layer formed in the region on the first conductive type base layer on which the second conductive type base layer is not formed; a gate insulation film formed on the inner surface of a trench formed between the second conductive type base layer and the insulation layer so as to separate them from each other and to reach the first conductive type base layer from the surface of the second conductive type base layer; a first conductive type source layer selectively formed on the surface of the second conductive type base layer in contact with the gate insulation film; a gate electrode formed in the trench and insulated from the first conductive type base layer, the second conductive type base layer, and the first conductive type source layer by the gate insulation film; a main electrode electrically connected to the first conductive type base layer and the second conductive type base layer; and a first conductive type or second conductive type floating layer formed on the bottom of the insulation layer.
摘要翻译：根据本发明的功率半导体器件包括：第一导电型基极层; 选择性地形成在所述第一导电型基底层上的第二导电型基底层; 形成在不形成第二导电型基底层的第一导电型基底层上的区域中的绝缘层; 形成在形成在第二导电型基极层和绝缘层之间的沟槽的内表面上以便将它们彼此分离并从第二导电类型基底的表面到达第一导电型基极的栅极绝缘膜层; 选择性地形成在与所述栅极绝缘膜接触的所述第二导电型基底层的表面上的第一导电型源极层; 形成在所述沟槽中的栅电极，通过所述栅极绝缘膜与所述第一导电型基极层，所述第二导电型基极层和所述第一导电型源极绝缘; 电连接到第一导电型基极层和第二导电型基极层的主电极; 以及形成在绝缘层的底部上的第一导电型或第二导电型浮动层。

17. 发明授权

US07361954B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07361954B2
公开(公告)日：2008-04-22
申请号：US11458234
申请日：2006-07-18
申请人： Koichi Sugiyama , Masakazu Yamaguchi
发明人： Koichi Sugiyama , Masakazu Yamaguchi
IPC分类号： H01L29/76
CPC分类号： H01L29/7397 , H01L29/0696 , H01L29/66348
摘要： Disclosed is a power semiconductor device, including: a gate electrode having a cross section having a length in a vertical direction, and having a shape extending in a direction orthogonal to the cross section; a gate insulating film surrounding the gate electrode; an n-type source layer positioning to face the gate electrode via the gate insulating film; a p-type base layer adjacent to the n-type source layer and positioning to face the gate electrode via the gate insulating film; an n-type base layer adjacent to the p-type base layer and positioning to face the gate electrode via the gate insulating film without being in contact with the n-type source layer; and a main electrode being in contact with the n-type source layer and the p-type base layer with plural lateral planes extending in a direction crossing the direction in which the gate electrode is extending.
摘要翻译：公开了一种功率半导体器件，包括：栅电极，其截面具有在垂直方向上的长度，并且具有沿与横截面正交的方向延伸的形状; 围绕所述栅电极的栅极绝缘膜; 通过栅极绝缘膜定位成面对栅电极的n型源极层; 与n型源极层相邻并且经由栅极绝缘膜定位成面对栅电极的p型基极层; 与p型基底层相邻的n型基底层，并且经由栅极绝缘膜定位成面对栅电极而不与n型源极接触; 以及与n型源极层和p型基极层接触的主电极，该多个侧面沿与栅电极延伸的方向交叉的方向延伸。

18. 发明申请

US20070210350A1 POWER SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SAME, AND METHOD FOR DRIVING SAME 有权
标题翻译：功率半导体器件，其制造方法及其驱动方法
公开(公告)号：US20070210350A1
公开(公告)日：2007-09-13
申请号：US11682670
申请日：2007-03-06
申请人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
发明人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L23/4824 , H01L29/0619 , H01L29/0696 , H01L29/41775 , H01L29/4236 , H01L29/66348 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
摘要翻译：功率半导体器件包括：半导体层，具有沿条形配置沿着第一方向延伸的沟槽; 掩埋在所述沟槽中的用于控制在所述半导体层中流动的电流的栅电极; 以及由具有比栅极电极更高的导电性的材料制成的栅极插塞，栅极插塞具有带状结构，并沿第一方向连接到栅电极。半导体层包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层，部分地设置在第一半导体层的上表面上; 第一导电类型的第三半导体层部分地设置在第二半导体层上; 以及设置在第一半导体层的下表面上的第二导电类型的第四半导体层。

19. 发明授权

US07772641B2 Power semiconductor device with a plurality of gate electrodes 有权
标题翻译：具有多个栅电极的功率半导体器件
公开(公告)号：US07772641B2
公开(公告)日：2010-08-10
申请号：US11682670
申请日：2007-03-06
申请人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
发明人： Ichiro Omura , Yoko Sakiyama , Hideki Nozaki , Atsushi Murakoshi , Masanobu Tsuchitani , Koichi Sugiyama , Tsuneo Ogura , Masakazu Yamaguchi , Tatsuo Naijo
IPC分类号： H01L29/80
CPC分类号： H01L29/7397 , H01L23/4824 , H01L29/0619 , H01L29/0696 , H01L29/41775 , H01L29/4236 , H01L29/66348 , H01L2924/0002 , H01L2924/00
摘要： A power semiconductor device includes: a semiconductor layer having a trench extending along a first direction in a stripe configuration; a gate electrode buried in the trench for controlling a current flowing in the semiconductor layer; and a gate plug made of a material having higher electrical conductivity than the gate electrode, the gate plug having the stripe configuration and being connected to the gate electrode along the first direction. The semiconductor layer includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type provided partially in an upper face of the first semiconductor layer; a third semiconductor layer of the first conductivity type provided partially on the second semiconductor layer; and a fourth semiconductor layer of the second conductivity type provided on a lower face of the first semiconductor layer.
摘要翻译：功率半导体器件包括：半导体层，具有沿条形配置沿着第一方向延伸的沟槽; 掩埋在所述沟槽中的用于控制在所述半导体层中流动的电流的栅电极; 以及由具有比栅极电极更高的导电性的材料制成的栅极插塞，栅极插塞具有带状结构，并沿第一方向连接到栅电极。半导体层包括：第一导电类型的第一半导体层; 第二导电类型的第二半导体层，部分地设置在第一半导体层的上表面上; 第一导电类型的第三半导体层部分地设置在第二半导体层上; 以及设置在第一半导体层的下表面上的第二导电类型的第四半导体层。

20. 发明授权

US07518197B2 Power semiconductor device 有权
标题翻译：功率半导体器件
公开(公告)号：US07518197B2
公开(公告)日：2009-04-14
申请号：US11437657
申请日：2006-05-22
申请人： Masakazu Yamaguchi
发明人： Masakazu Yamaguchi
IPC分类号： H01L27/088
CPC分类号： H01L29/0834 , H01L29/0619 , H01L29/7395 , H01L29/7397 , H01L29/8611
摘要： A power semiconductor device has a first base layer of first conductive type, a contact layer of first conductive type formed on a surface of the first base layer, a second base layer of first conductive layer which is formed on the surface of the first base layer at a side opposite to the first contact layer and has an impurity concentration higher than that of the first base layer, a second contact layer of second conductive type formed on the surface of the first base layer or the second base layer, and a junction termination region formed in vicinity of or in contact with outside in a horizontal direction of the second contact layer.
摘要翻译：功率半导体器件具有第一导电类型的第一基底层，形成在第一基底层的表面上的第一导电类型的接触层，形成在第一基底层的表面上的第一导电层的第二基底层在与第一接触层相对的一侧具有高于第一基底层的杂质浓度的第一接触层，形成在第一基底层或第二基底层的表面上的第二导电类型的第二接触层和接合终端在第二接触层的水平方向上形成在外部附近或与外部接触的区域。

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