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11. 发明授权

US4408306A Column and row erasable EEPROM 失效
标题翻译：列和行可擦除EEPROM
公开(公告)号：US4408306A
公开(公告)日：1983-10-04
申请号：US306120
申请日：1981-09-28
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： G11C14/00 , G11C16/02 , G11C16/06 , G11C16/08 , G11C16/12 , G11C16/16 , G11C16/32 , G11C17/00 , G11C11/40
CPC分类号： G11C16/32 , G11C16/08 , G11C16/12 , G11C16/16
摘要： An EEPROM has an array of memory elements arranged by row and column which is accessed by a decoder capable of selecting all columns while enabling a single row in response to one input and selecting one column while enabling all rows in response to another input, thereby selectively erasing one entire row or column.
摘要翻译： EEPROM具有由行和列排列的存储器元件阵列，其由能够选择所有列的解码器访问，而能够响应于一个输入启用单个行并选择一列，同时响应于另一个输入启用所有行，从而选择性地擦除整个行或列。

12. 发明授权

US4479203A Electrically erasable programmable read only memory cell 失效
标题翻译：电可擦除可编程只读存储单元
公开(公告)号：US4479203A
公开(公告)日：1984-10-23
申请号：US321855
申请日：1981-11-16
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： H01L27/112 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C7/00 , G11C11/40
CPC分类号： H01L27/115 , G11C16/0433
摘要： An electrically erasable programmable read only memory (EEPROM) cell has a floating gate transistor and a select transistor in series. A control gate of the select transistor extends to an area which overlies an extended portion of a floating gate of the floating gate transistor to form an erase window so that the EEPROM cell can be erased by application of an erase signal to the control gate of the select transistor.
摘要翻译：电可擦除可编程只读存储器（EEPROM）单元具有串联的浮栅晶体管和选择晶体管。选择晶体管的控制栅极延伸到覆盖浮置晶体管的浮动栅极的延伸部分的区域，以形成擦除窗口，从而可以通过向擦除窗口的控制栅极施加擦除信号来擦除EEPROM单元选择晶体管。

13. 发明授权

US4417154A Circuit for applying a high voltage signal to a fusible link 失效
标题翻译：用于将高电压信号施加到可熔链路的电路
公开(公告)号：US4417154A
公开(公告)日：1983-11-22
申请号：US346974
申请日：1982-02-08
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： G11C11/34 , G11C17/18 , G11C29/00 , G11C29/04 , H03K5/02 , H03K17/687 , G11C17/00
CPC分类号： G11C29/785 , G11C17/18 , H03K5/023
摘要： A fusible link is selectively opened by selectively applying a high voltage signal to a transistor in series with the fusible link while the high voltage signal is applied to the fusible link. A grounding circuit ensures that one terminal of the fusible link is coupled to ground in the absence of the high voltage signal. The grounding circuit can be used in conjunction with a plurality of means for selectively opening fusible links.
摘要翻译：通过选择性地将高电压信号施加到与可熔链路串联的晶体管，同时将高电压信号施加到可熔链路来选择性地打开熔断链路。接地电路确保在没有高电压信号的情况下可熔链路的一个端子耦合到地。接地电路可以与多个用于选择性地打开易熔链路的装置结合使用。

14. 发明授权

US4412309A EEPROM With bulk zero program capability 失效
标题翻译： EEPROM具有批量零程序功能
公开(公告)号：US4412309A
公开(公告)日：1983-10-25
申请号：US306119
申请日：1981-09-28
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： G11C14/00 , G11C11/41 , G11C16/08 , G11C16/16 , G11C16/32 , G11C17/00 , G11C11/40
CPC分类号： G11C16/08 , G11C16/16 , G11C16/32 , G11C2216/16 , G11C2216/18
摘要： An EEPROM which can erase an array of memory cells to all "1"s is capable of causing all of the cells of the array to assume all "0"s, also. The array of memory cells is arranged with one of said memory elements at the intersection of each of a plurality of rows and columns. The memory elements are characterized as assuming relatively high threshold voltage states in response to an erase voltage and relatively low threshold voltage states in response to a program voltage. All columns and rows are selected in order to apply the program voltage to all of the memory elements.
摘要翻译：可以将存储器单元阵列擦除为所有“1”的EEPROM能够使阵列的所有单元全部为“0”。存储单元的阵列与多个行和列中的每一个的相交处布置有一个所述存储元件。存储器元件的特征在于假定响应于编程电压而响应于擦除电压和相对低的阈值电压状态的相对高的阈值电压状态。选择所有列和行以便将程序电压施加到所有存储器元件。

15. 发明授权

US5339279A Block erasable flash EEPROM apparatus and method thereof 失效
标题翻译：块可擦除快闪EEPROM装置及其方法
公开(公告)号：US5339279A
公开(公告)日：1994-08-16
申请号：US57924
申请日：1993-05-07
申请人： Thomas R. Toms , Ann E. Harwood , Yoshiko K. Inoue , Clinton C. K. Kuo
发明人： Thomas R. Toms , Ann E. Harwood , Yoshiko K. Inoue , Clinton C. K. Kuo
IPC分类号： G11C16/16 , G11C16/30 , G11C11/34 , G11C7/00 , G11C8/00
CPC分类号： G11C16/16 , G11C16/30
摘要： A block erasable flash EEPROM (22) having a single array (68) which can be partitioned into one or more blocks (50-57). The same column decode/block select circuitry (66) is used to provide both column select signals (71) and block select signals (73). The number of blocks (50-57) and the size of each block (50-57) can be determined by the manufacturer during the manufacturing process. Each block (50-57) has a corresponding charge pump (80-87). Each charge pump (80-87) is capable of erasing a single block within the array (68). Each charge pump (80-87) has a variable capacitor (90-97). Each of the variable capacitors (90-97) can be sized according to the size of its corresponding block (50-57).
摘要翻译：具有可以被划分成一个或多个块（50-57）的单个阵列（68）的块可擦除快闪EEPROM（22）。相同的列解码/块选择电路（66）用于提供列选择信号（71）和块选择信号（73）。块（50-57）的数量和每个块的大小（50-57）可以由制造商在制造过程中确定。每个块（50-57）都有相应的电荷泵（80-87）。每个电荷泵（80-87）能够擦除阵列（68）内的单个块。每个电荷泵（80-87）具有可变电容器（90-97）。每个可变电容器（90-97）可以根据其相应块的尺寸（50-57）来定尺寸。

16. 发明授权

US5034923A Static RAM with soft defect detection 失效
标题翻译：具有软缺陷检测的静态RAM
公开(公告)号：US5034923A
公开(公告)日：1991-07-23
申请号：US283032
申请日：1988-12-05
申请人： Clinton C. K. Kuo , Ernest A. Carter
发明人： Clinton C. K. Kuo , Ernest A. Carter
IPC分类号： G11C29/02 , G11C29/50
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C29/50016 , G11C11/41 , G11C2029/5006
摘要： A static RAM includes test features which provide for the detection of soft defects which may cause a defective SRAM cell to behave as a functional DRAM cell. Provision is made for writing either a high or a low logic state to each bit line of the SRAM while not writing any value to its complementary bit line and for sensing the state of each bit line independently of the state of its complementary bit line. In addition, a current test is provided which detects soft defects by means of the increased inverter leakage current caused thereby. It is possible, by properly combining these tests, to reliably detect all soft defects, thereby assuring the data retention capability of the SRAM. This technique avoids the long hold time and/or high temperature test techniques used in the prior art.
摘要翻译：静态RAM包括提供检测软缺陷的测试特征，这可能导致有缺陷的SRAM单元表现为功能性DRAM单元。提供写入高或低逻辑状态到SRAM的每个位线，而不向其互补位线写入任何值，并且用于独立于其互补位线的状态来感测每个位线的状态。此外，提供了通过由此引起的增加的逆变器漏电流来检测软缺陷的电流测试。通过适当组合这些测试，可以可靠地检测所有的软缺陷，从而保证SRAM的数据保留能力。该技术避免了现有技术中使用的长的保持时间和/或高温测试技术。

17. 发明授权

US4758986A Single transistor cell for electrically-erasable programmable read-only memory and array thereof 失效
公开(公告)号：US4758986A
公开(公告)日：1988-07-19
申请号：US17118
申请日：1987-02-20
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： G11C16/04 , G11C13/00 , G11C11/40
CPC分类号： G11C16/0416
摘要： A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.

18. 发明授权

US4408305A Memory with permanent array division capability 失效
标题翻译：具有永久阵列分割能力的内存
公开(公告)号：US4408305A
公开(公告)日：1983-10-04
申请号：US305830
申请日：1981-09-28
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： G11C8/00 , G11C8/12 , G11C17/00 , G11C29/00 , G11C29/04 , G11C11/40
CPC分类号： G11C29/78 , G11C8/00 , G11C8/12
摘要： A memory can be divided to provide a reduced number of accessible memory elements. By selectively causing an individual address to always assume a predetermined logic state, the number of accessible memory elements is reduced by one half. The selection as to which half is accessible is achieved by applying to an array divider circuit the individual address signal data logic state which corresponds to the predetermined logic state then applying to the array divider circuit an array divider signal. The array divider circuit subsequently provides the individual address signal at the predetermined logic state effectively reducing the number of accessible memory elements by one half.
摘要翻译：可以划分存储器以提供可减少数量的可访问存储器元件。通过选择性地使单个地址始终采取预定的逻辑状态，可访问存储器元件的数量减少了一半。通过向阵列分频器电路施加与预定逻辑状态对应的单独地址信号数据逻辑状态，然后向阵列除法器电路施加阵列除法器信号，实现对哪一半可访问的选择。阵列分频器电路随后在预定的逻辑状态下提供单独的地址信号，有效地将可访问存储器元件的数量减少了一半。

19. 发明授权

US4975882A User programmable redundant memory 失效
标题翻译：用户可编程冗余存储器
公开(公告)号：US4975882A
公开(公告)日：1990-12-04
申请号：US429956
申请日：1989-10-30
申请人： Clinton C. K. Kuo , Ernest A. Carter , Joseph Jelemensky
发明人： Clinton C. K. Kuo , Ernest A. Carter , Joseph Jelemensky
IPC分类号： G11C29/00
CPC分类号： G11C29/808
摘要： A memory has a programmable circuit which allows a user to select an amount of redundancy the memory has varying from zero percent to one-hundred percent. A received address is compared by the circuit with a redundancy percentage control signal to determine if the address falls within a redundant portion of the memory. If so, a redundancy enable signal is asserted to allow the memory to utilize the redundant circuitry.
摘要翻译：存储器具有可编程电路，其允许用户选择存储器从0％变化到百分之百的冗余量。接收到的地址由电路与冗余百分比控制信号进行比较，以确定地址是否落在存储器的冗余部分内。如果是这样，则断言冗余使能信号以允许存储器利用冗余电路。

20. 发明授权

US4766473A Single transistor cell for electrically-erasable programmable read-only memory and array thereof 失效
标题翻译：用于电可擦除可编程只读存储器及其阵列的单晶体管单元
公开(公告)号：US4766473A
公开(公告)日：1988-08-23
申请号：US947213
申请日：1986-12-29
申请人： Clinton C. K. Kuo
发明人： Clinton C. K. Kuo
IPC分类号： H01L29/788 , H01L29/78
CPC分类号： H01L29/7885
摘要： A single transistor EEPROM cell comprises a source, a channel, a drain, a floating gate and a control gate. The control gate and the floating gate are co-extensive over the channel. Programming is achieved by charge injection from the channel and erasing is achieved by tunneling to the source. An array organization is disclosed which features a source/erase control line shared between two adjacent rows of the array, providing efficient byte-at-a-time erasing. An erasure scheme is disclosed which involves repetitive erase pulse-read-erase pulse cycles together with means for assuring complete erasure while preventing over-erasure from driving any cell in the array into depletion mode.
摘要翻译：单个晶体管EEPROM单元包括源极，沟道，漏极，浮动栅极和控制栅极。控制栅极和浮动栅极在通道上共同扩展。编程通过从信道进行电荷注入来实现，并且通过隧道到源来实现擦除。公开了一种阵列组织，其特征在于阵列的两个相邻行之间共享的源/擦除控制线，提供高效的字节同时擦除。公开了一种擦除方案，其涉及重复的擦除脉冲读取 - 擦除脉冲周期以及用于确保完全擦除的装置，同时防止过度擦除将阵列中的任何单元驱动为耗尽模式。

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