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11. 发明授权

US07812390B2 Semiconductor memory device with memory cells on multiple layers 有权
标题翻译：具有多层存储单元的半导体存储器件
公开(公告)号：US07812390B2
公开(公告)日：2010-10-12
申请号：US11777293
申请日：2007-07-13
申请人： Ki-Tae Park , Jung-Dal Choi , Jae-Sung Sim
发明人： Ki-Tae Park , Jung-Dal Choi , Jae-Sung Sim
IPC分类号： H01L25/065 , H01L27/115
CPC分类号： H01L27/11551 , G11C11/5621 , G11C16/0483 , G11C2211/5641 , H01L27/0688 , H01L27/105 , H01L27/11526 , H01L27/11529
摘要： A semiconductor memory device includes a first substrate having at least one string including a first select transistor, a second select transistor, and first memory cells connected in series between the first and second select transistors of the first substrate. The semiconductor memory device further includes a second substrate having at least one string including a first select transistor, a second select transistor, and second memory cells connected in series between the first and second select transistors of the second substrate. The number of the first memory cells of the at least one string of the first substrate is different from a number of the second memory cells of the at least one string of the second substrate. For example, the number of second memory cells may be less than the number of first memory cells.
摘要翻译：半导体存储器件包括具有包括第一选择晶体管，第二选择晶体管和串联连接在第一衬底的第一和第二选择晶体管之间的第一存储单元的至少一个串的第一衬底。半导体存储器件还包括具有至少一个串的第二衬底，该至少一个串包括串联连接在第二衬底的第一和第二选择晶体管之间的第一选择晶体管，第二选择晶体管和第二存储单元。第一衬底的至少一个串的第一存储器单元的数量与第二衬底的至少一个串的第二存储单元的数量不同。例如，第二存储器单元的数量可以小于第一存储器单元的数量。

12. 发明授权

US07773422B2 3-level non-volatile semiconductor memory device and method of driving the same 有权
标题翻译： 3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US07773422B2
公开(公告)日：2010-08-10
申请号：US12052666
申请日：2008-03-20
申请人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
发明人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
IPC分类号： G11C11/04
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

13. 发明申请

US20090135647A1 NAND FLASH MEMORY DEVICES HAVING SHIELDING LINES BETWEEN WORDLINES AND SELECTION LINES 有权
标题翻译：具有屏幕线和选择线之间的屏蔽线的NAND闪存存储器件
公开(公告)号：US20090135647A1
公开(公告)日：2009-05-28
申请号：US12358009
申请日：2009-01-22
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A method of programming a flash memory includes applying a shielding voltage to at least one shielding line, which is interposed between a plurality of wordlines and a selection line and operable to reduce capacitance-coupling between the wordline and the selection line during the programming operation, and applying a program voltage to memory cells through one of the wordlines.
摘要翻译：一种对闪速存储器进行编程的方法包括：对至少一个屏蔽线施加屏蔽电压，该屏蔽线介于多个字线和选择线之间，并且可操作以在编程操作期间减小字线和选择线之间的电容耦合，以及通过字线之一向存储器单元施加编程电压。

14. 发明申请

US20090097326A1 NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME 有权
标题翻译：具有存储单元的NAND闪速存储器件及其操作方法
公开(公告)号：US20090097326A1
公开(公告)日：2009-04-16
申请号：US12340250
申请日：2008-12-19
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

15. 发明授权

US07366033B2 3-level non-volatile semiconductor memory device and method of driving the same 失效
标题翻译： 3级非易失性半导体存储器件及其驱动方法
公开(公告)号：US07366033B2
公开(公告)日：2008-04-29
申请号：US11460580
申请日：2006-07-27
申请人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
发明人： Ki-Tae Park , Jung-Dal Choi , Sung-Kyu Jo
IPC分类号： G11C7/00
CPC分类号： G11C11/5628 , G11C11/5642 , G11C16/10 , G11C16/24
摘要： A page buffer for a non-volatile semiconductor memory device includes a switch configured to couple a first bitline coupled to a first memory cell to a second bitline coupled to a second memory cell, a first latch block coupled to the first bitline and configured to transfer a first latch data to the first memory cell, and a second latch block coupled to the second bitline and the first latch block, and configured to transfer a second latch data to the second memory cell.
摘要翻译：用于非易失性半导体存储器件的页面缓冲器包括被配置为将耦合到第一存储器单元的第一位线耦合到耦合到第二存储器单元的第二位线的开关，耦合到第一位线并被配置为传送的第一锁存块向第一存储器单元提供第一锁存数据，以及耦合到第二位线和第一锁存块的第二锁存块，并且被配置为将第二锁存数据传送到第二存储器单元。

16. 发明申请

US20080074923A1 FLASH MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME 有权
标题翻译：闪存存储器件及其编程方法
公开(公告)号：US20080074923A1
公开(公告)日：2008-03-27
申请号：US11855978
申请日：2007-09-14
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/0483
摘要： A flash memory device and a method of programming the same are disclosed. The flash memory device includes an array of memory cells intersected by a plurality of bit lines and a plurality of word lines. A page buffer circuit includes a plurality of latches coupled to an even virtual bit line and an odd virtual bitline. The page buffer circuit is configured to load data into the array of memory cells responsive to a select circuit, which is structured to electrically couple at least some of the bit lines to the plurality of latches of the page buffer circuit.
摘要翻译：公开了一种闪存器件及其编程方法。闪存器件包括由多个位线和多个字线相交的存储器单元的阵列。页面缓冲电路包括耦合到偶数虚拟位线和奇数虚拟位线的多个锁存器。页面缓冲器电路被配置为响应于选择电路将数据加载到存储器单元阵列中，该选择电路被构造为将至少一些位线电耦合到页缓冲器电路的多个锁存器。

17. 发明申请

US20080007999A1 Nonvolatile memory device with NAND cell strings 有权
标题翻译：具有NAND单元串的非易失性存储器件
公开(公告)号：US20080007999A1
公开(公告)日：2008-01-10
申请号：US11657696
申请日：2007-01-25
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/3418
摘要： A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.
摘要翻译：非易失性存储器件包括存储单元阵列，其中多个存储单元晶体管被分成多个擦除块。多个擦除块通过虚拟字线彼此分离。在多个块之一的擦除操作期间，以耦合禁止电压驱动将多个块中的一个与其它擦除块分开的虚拟字线。

18. 发明申请

US20060208302A1 Non-volatile memory device having charge trap layer and method of fabricating the same 审中-公开
标题翻译：具有电荷陷阱层的非易失性存储器件及其制造方法
公开(公告)号：US20060208302A1
公开(公告)日：2006-09-21
申请号：US11354535
申请日：2006-02-15
申请人： Yoo-Cheol Shin , Jung-Dal Choi , Ki-Tae Park , Jong-Sun Sel
发明人： Yoo-Cheol Shin , Jung-Dal Choi , Ki-Tae Park , Jong-Sun Sel
IPC分类号： H01L29/76
CPC分类号： H01L29/66833 , H01L29/792
摘要： A non-volatile memory device having a charge trap layer and a method of fabricating the same are provided. The non-volatile memory device includes a semiconductor substrate having an active region and a field region in contact with the active region. A trench isolation layer is formed within the semiconductor substrate field region to define the active region and has a protrusion higher than a top surface of the semiconductor substrate active region. A memory storage pattern is formed which crosses and extends from the semiconductor substrate active region to cover sidewalls of the protrusion of the trench isolation layer. A gate electrode is formed on the memory storage pattern and extends upward from the trench isolation layer.
摘要翻译：提供了具有电荷陷阱层的非易失性存储器件及其制造方法。非易失性存储器件包括具有有源区和与有源区接触的场区的半导体衬底。沟槽隔离层形成在半导体衬底场区内，以限定有源区，并具有高于半导体衬底有源区的顶表面的突起。形成存储器存储图案，其跨越并从半导体衬底有源区域延伸以覆盖沟槽隔离层的突起的侧壁。栅电极形成在存储器存储图案上并从沟槽隔离层向上延伸。

19. 发明申请

US20110090738A1 NAND FLASH MEMORY DEVICE HAVING DUMMY MEMORY CELLS AND METHODS OF OPERATING SAME 有权
标题翻译：具有存储单元的NAND闪速存储器件及其操作方法
公开(公告)号：US20110090738A1
公开(公告)日：2011-04-21
申请号：US12977419
申请日：2010-12-23
申请人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
发明人： Ki-Tae Park , Jung-Dal Choi , Jong-Sun Sel , Yoo-Cheol Shin
IPC分类号： G11C16/12
CPC分类号： G11C16/0483 , G11C16/107 , G11C16/12 , G11C16/3445
摘要： A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.
摘要翻译： NAND闪速存储器件包括控制电路，其被配置为在编程操作期间将第一字线电压施加到多个串联存储器单元中的未选择的电压，第二字线电压大于第一字线电压到多个存储单元中的一个选择的一个，以及比第一字线电压低的第三字线电压到与多个存储单元串联连接的虚拟存储单元。在其他实施例中，控制电路被配置为在与每个擦除操作之间的每个擦除操作之前和/或之后对与其串联的多个存储器单元进行编程。在其他实施例中，控制电路被配置为在擦除与其串联连接的多个存储器单元时，放弃擦除伪存储器单元。

20. 发明授权

US07830724B2 Nonvolatile memory device with NAND cell strings 有权
标题翻译：具有NAND单元串的非易失性存储器件
公开(公告)号：US07830724B2
公开(公告)日：2010-11-09
申请号：US12636980
申请日：2009-12-14
申请人： Ki-Tae Park , Jung-Dal Choi
发明人： Ki-Tae Park , Jung-Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C8/08 , G11C8/14 , G11C16/0483 , G11C16/3418
摘要： A nonvolatile memory device comprises a memory cell array wherein a plurality of memory cell transistors are divided into multiple erase blocks. The multiple erase blocks are separated from each other by dummy word lines. During an erase operation of one of the multiple blocks, a dummy word line separating the one of the multiple blocks from other erase blocks is driven with a coupling inhibition voltage.
摘要翻译：非易失性存储器件包括存储单元阵列，其中多个存储单元晶体管被分成多个擦除块。多个擦除块通过虚拟字线彼此分离。在多个块之一的擦除操作期间，以耦合禁止电压驱动将多个块中的一个与其它擦除块分开的虚拟字线。

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