专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07698522B1 Method and apparatus for linear address based page level security scheme to determine current security context 有权
标题翻译：基于线性地址的页面级安全方案的方法和装置，用于确定当前的安全上下文
公开(公告)号：US07698522B1
公开(公告)日：2010-04-13
申请号：US10044667
申请日：2002-01-11
申请人： Brian C. Barnes , Geoffrey S. Strongin , Rodney W. Schmidt
发明人： Brian C. Barnes , Geoffrey S. Strongin , Rodney W. Schmidt
IPC分类号： G06F13/00 , G06F9/26 , H04L29/06
CPC分类号： G06F12/1491 , G06F12/145
摘要： A method and an apparatus for performing a virtual address based memory access. A software object is executed. A security level for the software object is established. A virtual address based memory access is performed using at least one of the security levels. The function of the object is executed based upon the virtual address based memory access.
摘要翻译：一种用于执行基于虚拟地址的存储器访问的方法和装置。执行软件对象。建立软件对象的安全级别。使用至少一个安全级别来执行基于虚拟地址的存储器访问。基于基于虚拟地址的存储器访问来执行对象的功能。

12. 发明授权

US07571318B2 Method and apparatus for improved security in a data processor 有权
标题翻译：用于提高数据处理器安全性的方法和装置
公开(公告)号：US07571318B2
公开(公告)日：2009-08-04
申请号：US10107633
申请日：2002-03-27
申请人： Geoffrey S. Strongin , Brian C. Barnes , Rodney Schmidt
发明人： Geoffrey S. Strongin , Brian C. Barnes , Rodney Schmidt
IPC分类号： H04L29/06 , G06F15/00
CPC分类号： G06F21/52 , G06F12/145 , G06F12/1491 , G06F21/79
摘要： A method and apparatus for controlling access to segments of memory having security data stored therein is provided. A security check unit maintains information for a plurality of segments of memory regarding whether each of these plurality of segments has secure data stored therein. A hint directory maintains information regarding whether any of a plurality of these segments has secure data stored therein. The hint directory is capable of bypassing the security check unit when it receives an address that falls within a plurality of the segments that have been indicated as being free from secure data. When the hint directory determines that a received address falls within one of a plurality of segments that contain secure data, then the address is passed to the security check unit for a closer examination.
摘要翻译：提供一种用于控制对其中存储有安全数据的存储器段的访问的方法和装置。安全检查单元维护关于这些多个段中的每一个是否存储有安全数据的存储器的多个段的信息。提示目录维护关于多个这些段中的任何一个是否具有存储在其中的安全数据的信息。提示目录在接收到已经被指示为没有安全数据的多个段内的地址时能够绕过安全检查单元。当提示目录确定接收到的地址落在包含安全数据的多个段中的一个段内时，该地址被传递到安全检查单元以进行仔细检查。

13. 发明授权

US5944816A Microprocessor configured to execute multiple threads including interrupt service routines 失效
标题翻译：配置为执行多个线程的微处理器，包括中断服务程序
公开(公告)号：US5944816A
公开(公告)日：1999-08-31
申请号：US649809
申请日：1996-05-17
申请人： Drew J. Dutton , David S. Christie , Brian C. Barnes
发明人： Drew J. Dutton , David S. Christie , Brian C. Barnes
IPC分类号： G06F9/38 , G06F9/46 , G06F9/48 , G06F9/30
CPC分类号： G06F9/4812 , G06F9/3851 , G06F9/3885 , G06F9/462
摘要： A microprocessor including a context file configured to store multiple contexts is provided. The microprocessor may execute multiple threads, each thread having its own context within the microprocessor. In one embodiment, the present microprocessor is capable of executing at least two threads concurrently: a task and an interrupt service routine. Interrupt service routines may be executed without disturbing a task's context and without performing a context save operation. Instead, the interrupt service routine accesses a context which is independent of the context of the task. In another embodiment, the context file includes multiple interrupt service routine contexts. Multiple ISR context storages allow for nested interrupts to be performed concurrently. In yet another embodiment, the microprocessor is configured to execute multiple tasks and multiple interrupt service routines concurrently. Multiple tasks may be executed concurrently by the microprocessor in addition to executing multiple interrupt service routines concurrently. In still another embodiment, the microprocessor includes a primary context and multiple local context storages coupled to each of its execution units. A given execution unit may execute instructions referencing the primary context or the local context connected thereto.
摘要翻译：提供了一种包括配置为存储多个上下文的上下文文件的微处理器。微处理器可以执行多个线程，每个线程在微处理器内具有其自己的上下文。在一个实施例中，本微处理器能够同时执行至少两个线程：任务和中断服务程序。可以执行中断服务例程而不干扰任务的上下文，而不执行上下文保存操作。相反，中断服务例程访问独立于任务上下文的上下文。在另一个实施例中，上下文文件包括多个中断服务例程上下文。多个ISR上下文存储允许同时执行嵌套中断。在另一个实施例中，微处理器被配置为同时执行多个任务和多个中断服务程序。除了同时执行多个中断服务程序之外，微处理器可以同时执行多个任务。在另一个实施例中，微处理器包括耦合到其每个执行单元的主上下文和多个本地上下文存储器。给定的执行单元可以执行引用主上下文或与其连接的本地上下文的指令。

14. 发明授权

US5136694A Method and apparatus facilitating communication between two keyboards and a single processor 失效
标题翻译：促进两个键盘和单个处理器之间的通信的方法和装置
公开(公告)号：US5136694A
公开(公告)日：1992-08-04
申请号：US334841
申请日：1989-04-07
申请人： Steven L. Belt , Mark A. Ruthenbeck , Mark J. Foster , Brian C. Barnes , Randy J. VanderHeyden
发明人： Steven L. Belt , Mark A. Ruthenbeck , Mark J. Foster , Brian C. Barnes , Randy J. VanderHeyden
IPC分类号： G06F3/02
CPC分类号： G06F3/0227 , G06F3/021
摘要： A computing device includes a system control processor, a built-in keyboard having a plurality of keys, a connector which facilitates connection of an external keyboard or keypad to the device, an electronic switch which is controlled by the internal keyboard processor and can electrically couple the connector to the system control processor. The internal keyboard processor monitors signals from the system control processor, connector and internal keyboard keys in order to open and close the analog switch so as to facilitate transfers between the system control processor and the internal keyboard through itself, and transfers between the system control processor and an external keyboard through the electronic switch.
摘要翻译：计算设备包括系统控制处理器，具有多个键的内置键盘，便于将外部键盘或小键盘连接到设备的连接器，由内部键盘处理器控制并可以电耦合的电子开关连接到系统控制处理器。内部键盘处理器监视来自系统控制处理器，连接器和内部键盘键的信号，以便打开和关闭模拟开关，以便于自身在系统控制处理器和内部键盘之间传输，并在系统控制处理器和通过电子开关的外部键盘。

15. 发明授权

US07739498B2 Method and apparatus for multi-table accessing of input/output devices using target security 有权
标题翻译：使用目标安全性对输入/输出设备进行多表访问的方法和装置
公开(公告)号：US07739498B2
公开(公告)日：2010-06-15
申请号：US10047188
申请日：2002-01-15
申请人： Brian C. Barnes , Geoffrey S. Strongin , Rodney W. Schmidt
发明人： Brian C. Barnes , Geoffrey S. Strongin , Rodney W. Schmidt
IPC分类号： H04L9/32
CPC分类号： G06F12/1491
摘要： A method and an apparatus for performing an I/O device access using targeted security. A software object is executed. A security level for the software object is established. A multi-table input/output (I/O) space access is performed using at least one of the security levels. The function of the object is executed.
摘要翻译：一种使用目标安全性执行I / O设备访问的方法和装置。执行软件对象。建立软件对象的安全级别。使用至少一个安全级别来执行多表输入/输出（I / O）空间访问。执行对象的功能。

16. 发明授权

US07426644B1 System and method for handling device accesses to a memory providing increased memory access security 有权
标题翻译：用于处理对存储器的设备访问的系统和方法，其提供增加的存储器访问安全性
公开(公告)号：US07426644B1
公开(公告)日：2008-09-16
申请号：US10011151
申请日：2001-12-05
申请人： Geoffrey S. Strongin , Brian C. Barnes , Rodney W. Schmidt
发明人： Geoffrey S. Strongin , Brian C. Barnes , Rodney W. Schmidt
IPC分类号： G06F21/00 , G06F21/22
CPC分类号： G06F12/1441 , G06F12/1491
摘要： A host bridge is described including a memory controller and a security check unit. The memory controller is adapted for coupling to a memory storing data arranged within a multiple memory pages. The memory controller receives memory access signals (e.g., during a memory access), and responds to the memory access signals by accessing the memory. The security check unit receives the memory access signals, wherein the memory access signals convey a physical address within a target memory page. The security check unit uses the physical address to access one or more security attribute data structures located in the memory to obtain a security attribute of the target memory page. The security check unit provides the memory access signals to the memory controller dependent upon the security attribute of the target memory page. A computer system is described including a memory storing data arranged within a multiple memory pages, a device operably coupled to the memory and configurable to produce memory access signals, the above described host bridge. The computer system may have, for example, a central processing unit (CPU) including a memory management unit (MMU) operably coupled to the memory and configured to manage the memory. The memory management unit (MMU) may manage the memory such that the memory stores the data arranged within the multiple memory pages. A method is disclosed for providing access security for a memory used to store data arranged within a multiple memory pages.
摘要翻译：描述了主桥，包括存储器控制器和安全检查单元。存储器控制器适于耦合到存储多个存储器页中布置的数据的存储器。存储器控制器接收存储器访问信号（例如，在存储器访问期间），并且通过访问存储器来响应存储器访问信号。安全检查单元接收存储器访问信号，其中存储器访问信号传达目标存储器页面内的物理地址。安全检查单元使用物理地址访问位于存储器中的一个或多个安全属性数据结构，以获得目标存储器页面的安全属性。安全检查单元根据目标存储器页面的安全属性向存储器控制器提供存储器访问信号。描述了一种计算机系统，包括存储布置在多个存储器页内的数据的存储器，可操作地耦合到存储器并且可配置为产生存储器访问信号的设备，上述主机桥。计算机系统可以具有例如包括可操作地耦合到存储器并被配置为管理存储器的存储器管理单元（MMU）的中央处理单元（CPU）。存储器管理单元（MMU）可以管理存储器，使得存储器存储布置在多个存储器页面中的数据。公开了一种用于提供用于存储布置在多个存储器页内的数据的存储器的访问安全性的方法。

17. 发明授权

US07325250B1 Method and apparatus for preventing radio communication system access by an unauthorized modem 失效
标题翻译：用于防止未经授权的调制解调器的无线电通信系统接入的方法和装置
公开(公告)号：US07325250B1
公开(公告)日：2008-01-29
申请号：US09901421
申请日：2001-07-09
申请人： Michael Barclay , Brian C. Barnes , Terry L. Cole , Rodney Schmidt , David W. Smith , Geoffrey S. Strongin
发明人： Michael Barclay , Brian C. Barnes , Terry L. Cole , Rodney Schmidt , David W. Smith , Geoffrey S. Strongin
IPC分类号： G06F17/00 , H04L9/00 , H04L1/00 , H04M1/66 , H04B7/00 , H04B1/02
CPC分类号： H04W12/08 , H04W92/10
摘要： A method and apparatus for preventing radio communication system access by an unauthorized modem. The apparatus comprises a signal detector that determines if an authorization signal has been received from the base station within a specified period of time. The authorization signal authorizes the apparatus to communicate with the base station. A transmitter transmits information to the base station, and a controller disables the transmitter of the apparatus providing that the authorization signal has not been received within the specified period of time.
摘要翻译：一种用于防止未经授权的调制解调器接入无线电通信系统的方法和装置。该装置包括信号检测器，该信号检测器确定在指定的时间段内是否已经从基站接收到授权信号。授权信号授权设备与基站进行通信。发射机向基站发送信息，并且控制器禁止设备的发射机，只要在指定的时间段内没有接收到授权信号。

18. 发明授权

US06378023B1 Interrupt descriptor cache for a microprocessor 失效
标题翻译：微处理器的中断描述符缓存
公开(公告)号：US06378023B1
公开(公告)日：2002-04-23
申请号：US09481005
申请日：2000-01-10
申请人： David S. Christie , Brian C. Barnes
发明人： David S. Christie , Brian C. Barnes
IPC分类号： G06F1324
CPC分类号： G06F13/24 , G06F12/0875
摘要： An interrupt descriptor cache for a microprocessor is provided which is configured to store interrupt information associated with a plurality of interrupt vectors. Prior to fetching interrupt information from a main memory of a computer system, the microprocessor searches the interrupt descriptor cache. If the interrupt information is stored therein, the address of the interrupt service routine is formed from the stored interrupt information instead of fetching the interrupt information from main memory. The interrupt descriptor cache is additionally configured to monitory memory accesses for updates to the interrupt information stored therein. If a memory location storing interrupt information is updated, then the interrupt descriptor cache invalidates any storage locations which may be storing the information.
摘要翻译：提供了一种用于微处理器的中断描述符缓存器，其被配置为存储与多个中断向量相关联的中断信息。在从计算机系统的主存储器获取中断信息之前，微处理器搜索中断描述符缓存。如果中断信息存储在其中，则中断服务程序的地址由存储的中断信息形成，而不是从主存储器取出中断信息。中断描述符缓存另外被配置为对存储在其中的中断信息的更新的监控存储器访问。如果更新存储中断信息的存储器位置，则中断描述符缓存使存储信息的任何存储位置无效。

19. 发明授权

US5727227A Interrupt coprocessor configured to process interrupts in a computer system 失效
标题翻译：中断协处理器配置为处理计算机系统中的中断
公开(公告)号：US5727227A
公开(公告)日：1998-03-10
申请号：US559659
申请日：1995-11-20
申请人： Rodney W. Schmidt , Brian C. Barnes
发明人： Rodney W. Schmidt , Brian C. Barnes
IPC分类号： G06F9/38 , G06F9/46 , G06F13/24 , G06F1/00
CPC分类号： G06F13/24 , G06F9/3879 , G06F9/462
摘要： A computer system employing an interrupt coprocessor is provided. The interrupt coprocessor is signaled by an interrupt controller to service a particular interrupt request. The interrupt coprocessor may include limited functionality, such that if a particular interrupt request is beyond the capabilities of the interrupt coprocessor, the microprocessor is interrupted. Context saves may be avoided in the interrupt coprocessor. Interrupt latency is reduced, as well as interruption of one or more main microprocessors in the computer system. Several embodiments are shown with a range of interrupt servicing capabilities. A data pump is shown, which is configured to transfer data from a source to a destination. A microcontroller is shown, which may manipulate the data as it is moved from source to destination or access the interrupting device to determine the service needed. Finally, a microprocessor similar to the main microprocessors of the computer system is shown. The microprocessor is capable of accessing system resources in a similar fashion to the main microprocessor, and therefore is capable of performing all interrupt servicing functions.
摘要翻译：提供了一种采用中断协处理器的计算机系统。中断协处理器由中断控制器发出信号，以服务于特定的中断请求。中断协处理器可以包括有限的功能，使得如果特定中断请求超出了中断协处理器的能力，则微处理器被中断。在中断协处理器中可以避免上下文保存。中断延迟减少，以及计算机系统中一个或多个主要微处理器的中断。示出了具有一定范围的中断服务能力的几个实施例。示出了数据泵，其被配置为将数据从源传送到目的地。示出了微控制器，其可以在数据从源移动到目的地时操纵数据，或者访问中断设备以确定所需的服务。最后，显示了类似于计算机系统的主要微处理器的微处理器。微处理器能够以与主微处理器相似的方式访问系统资源，因此能够执行所有中断服务功能。

20. 发明授权

US5280621A Personal computer having dedicated processors for peripheral devices interconnected to the CPU by way of a system control processor 失效
标题翻译：具有通过系统控制处理器与CPU互连的外围设备的专用处理器的个人计算机
公开(公告)号：US5280621A
公开(公告)日：1994-01-18
申请号：US19997
申请日：1993-02-17
申请人： Brian C. Barnes , Mark J. Foster , Lloyd W. Gauthier , Saifee Fakhruddin , David J. DeLisle , David R. Veit
发明人： Brian C. Barnes , Mark J. Foster , Lloyd W. Gauthier , Saifee Fakhruddin , David J. DeLisle , David R. Veit
IPC分类号： G06F13/12
CPC分类号： G06F13/124
摘要： A plurality of processors form a network used to communicate with one or more peripheral devices and the system control processor. One processor is dedicated to at least one peripheral device. Since the system control processor is not burdened with the relatively slow communications protocol with the peripheral devices, it is free to do other tasks which improves the overall system performance. Communication protocol between the dedicated processors allows for local and global communication.
摘要翻译：多个处理器形成用于与一个或多个外围设备和系统控制处理器进行通信的网络。一个处理器专用于至少一个外围设备。由于系统控制处理器不会与外围设备相对较慢的通信协议负担，因此可以自由地执行其他任务，从而提高整个系统的性能。专用处理器之间的通信协议允许本地和全球通信。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式