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11. 发明授权

US07757032B2 Computer system bus bridge 失效
标题翻译：计算机系统总线桥
公开(公告)号：US07757032B2
公开(公告)日：2010-07-13
申请号：US12195134
申请日：2008-08-20
申请人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36 , G06F3/00
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.
摘要翻译：高速计算机总线与高速输出总线之间的总线桥。优选实施例是用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与输出高速接口（MPI）之间的总线桥。另一个优选实施例是多芯片模块上的总线收发器中的总线桥。

12. 发明授权

US07330925B2 Transaction flow control mechanism for a bus bridge 有权
标题翻译：总线桥的交易流控制机制
公开(公告)号：US07330925B2
公开(公告)日：2008-02-12
申请号：US11064722
申请日：2005-02-24
申请人： Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36 , G06F12/00
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A transaction flow control mechanism is disclosed for a bus bridge in a high speed computer system with a high speed interface for a graphics processor. A preferred embodiment provides a flow control mechanism for the bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and a high speed interface. A preferred embodiment of the invention is a bus transceiver on a multi-chip module.
摘要翻译：公开了一种用于具有用于图形处理器的高速接口的高速计算机系统中的总线桥的事务流控制机制。优选实施例提供了用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与高速接口之间的总线桥的流量控制机制。本发明的优选实施例是多芯片模块上的总线收发器。

13. 发明授权

US07469312B2 Computer system bus bridge 失效
标题翻译：计算机系统总线桥
公开(公告)号：US07469312B2
公开(公告)日：2008-12-23
申请号：US11064568
申请日：2005-02-24
申请人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36 , G06F3/00
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A method for bridging between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a method for bridging between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI).
摘要翻译：一种用于在高速计算机处理器总线和高速输出总线之间桥接的方法。优选实施例是用于桥接国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线和输出高速接口（MPI）之间的桥接方法。

14. 发明授权

US07275125B2 Pipeline bit handling circuit and method for a bus bridge 失效
标题翻译：一种总线桥管道位处理电路及方法
公开(公告)号：US07275125B2
公开(公告)日：2007-09-25
申请号：US11064744
申请日：2005-02-24
申请人： Robert Allen Drehmel , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Robert Allen Drehmel , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36 , G06F7/38 , G06F13/00
CPC分类号： G06F13/4027 , G06F12/0831
摘要： A circuit and method to provide pipeline bit handling across a bus bridge between two different buses. In a preferred embodiment, the pipeline bit handling circuit provides rule enforcement for a P-bit address modifier across a bus bridge between two different buses with different rules for the P-bit address modifier. In a bus domain where pipeline transactions are allowed if the P-Bit is asserted and are not allowed if the P-Bit is not asserted, embodiments herein allow a master bus device to ensure that all bus devices will see a P=0 command with a defined minimum spacing to any other P=0 command. The required separation for P=0 commands is maintained within the bus bridge. In the preferred embodiments, the separation between P=0 commands is maintained by immediately retrying P=0 commands rather than spacing snoop requests.
摘要翻译：一种用于在两条不同总线之间的总线桥上提供流水线位处理的电路和方法。在优选实施例中，流水线位处理电路为P位地址修改器具有不同规则的两个不同总线之间的总线桥上的P位地址修改器提供规则强制。在一个总线域中，如果P位被断言，允许流水线事务被允许，并且如果P位未被置位则不允许流水线事务，这里的实施例允许主总线设备确保所有总线设备将看到P = 0命令，与任何其他P = 0命令的定义的最小间距。在总线桥内保持P = 0命令所需的间隔。在优选实施例中，通过立即重试P = 0命令而不是间隔窥探请求来保持P = 0命令之间的间隔。

15. 发明申请

US20080307147A1 COMPUTER SYSTEM BUS BRIDGE 失效
标题翻译：计算机系统总线桥
公开(公告)号：US20080307147A1
公开(公告)日：2008-12-11
申请号：US12195134
申请日：2008-08-20
申请人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Giora Biran , Robert Allen Drehmel , Robert Spencer Horton , Mark E. Kautzman , Jamie Randall Kuesel , Ming-i Mark Lin , Eric Oliver Mejdrich , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36 , G06F12/08 , G06F13/00
CPC分类号： G06F13/4059 , G06F12/0831
摘要： A bus bridge between a high speed computer processor bus and a high speed output bus. The preferred embodiment is a bus bridge between a GPUL bus for a GPUL PowerPC microprocessor from International Business Machines Corporation (IBM) and an output high speed interface (MPI). Another preferred embodiment is a bus bridge in a bus transceiver on a multi-chip module.
摘要翻译：高速计算机总线与高速输出总线之间的总线桥。优选实施例是用于来自国际商业机器公司（IBM）的GPUL PowerPC微处理器的GPUL总线与输出高速接口（MPI）之间的总线桥。另一个优选实施例是多芯片模块上的总线收发器中的总线桥。

16. 发明授权

US07234017B2 Computer system architecture for a processor connected to a high speed bus transceiver 有权
标题翻译：用于连接到高速总线收发器的处理器的计算机系统架构
公开(公告)号：US07234017B2
公开(公告)日：2007-06-19
申请号：US11064745
申请日：2005-02-24
申请人： Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
发明人： Giora Biran , Matthew Adam Cushing , Robert Allen Drehmel , Allen James Gavin , Mark E. Kautzman , Jamie Randall Kuesel , Ming-I Mark Lin , David Arnold Luick , James Anthony Marcella , Mark Owen Maxson , Eric Oliver Mejdrich , Adam James Muff , Clarence Rosser Ogilvie , Charles S. Woodruff
IPC分类号： G06F13/36
CPC分类号： G06F13/4059
摘要： A high speed computer processor system has a high speed interface for a graphics processor. A preferred embodiment combines a PowerPC microprocessor called the Giga-Processor Ultralite (GPUL) 110 from International Business Machines Corporation (IBM) with a high speed interface on a multi-chip module.
摘要翻译：高速计算机处理器系统具有用于图形处理器的高速接口。优选实施例将来自国际商业机器公司（IBM）的称为Giga-Processor Ultralite（GPUL）110的PowerPC微处理器与多芯片模块上的高速接口相结合。

17. 发明授权

US07480888B1 Design structure for facilitating engineering changes in integrated circuits 失效
标题翻译：集成电路工程变更的设计结构
公开(公告)号：US07480888B1
公开(公告)日：2009-01-20
申请号：US12124771
申请日：2008-05-21
申请人： Clarence Rosser Ogilvie , Charles B. Winn , David Wills Milton , Kenneth Anthony Lauricella , Nitin Sharma , Paul Mark Schanely , Robert Dov Herzl , Robert Spencer Horton , Tad Jeffrey Wilder , Douglas P. Nadeau
发明人： Clarence Rosser Ogilvie , Charles B. Winn , David Wills Milton , Kenneth Anthony Lauricella , Nitin Sharma , Paul Mark Schanely , Robert Dov Herzl , Robert Spencer Horton , Tad Jeffrey Wilder , Douglas P. Nadeau
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： A design structure embodied in a machine-readable medium is disclosed in one embodiment of the invention as including a flexible logic block to facilitate engineering changes at selected locations within an IC. The flexible logic block has a consistent and identifiable structure such that a simple automated process may be used to reconfigure the structure to perform different logical operations. In certain embodiments, the flexible logic block includes a circuit, such as a multiplexer, having multiple inputs and at least one output. A metal interconnect structure is coupled to the inputs and enables connection of each of the inputs to one of several electrical potentials using a focused-ion-beam (FIB) tool. In this way, the circuit may be configured to perform different logical operations after components in the IC exist in hardware.
摘要翻译：在本发明的一个实施例中公开了体现在机器可读介质中的设计结构，包括用于促进在IC内的选定位置进行工程变更的灵活逻辑块。灵活的逻辑块具有一致且可识别的结构，使得可以使用简单的自动化过程来重新配置结构以执行不同的逻辑操作。在某些实施例中，柔性逻辑块包括具有多个输入和至少一个输出的电路，例如多路复用器。金属互连结构耦合到输入端，并且能够使用聚焦离子束（FIB）工具将每个输入端连接到几个电势之一。以这种方式，电路可以被配置为在硬件中存在IC中的部件之后执行不同的逻辑操作。

18. 发明授权

US07787577B2 Asynchronous interface methods and apparatus 失效
标题翻译：异步接口方法和设备
公开(公告)号：US07787577B2
公开(公告)日：2010-08-31
申请号：US12013958
申请日：2008-01-14
申请人： Seetharam Gundurao , Kenneth Anthony Lauricella , Clarence Rosser Ogilvie , Nishant Sharma , Richard N. Wilson
发明人： Seetharam Gundurao , Kenneth Anthony Lauricella , Clarence Rosser Ogilvie , Nishant Sharma , Richard N. Wilson
IPC分类号： H04L7/00
CPC分类号： H03M9/00 , H04L7/0041 , H04L25/14
摘要： In a first aspect of the invention, a first method is provided for aligning signals from a first receiver located in a first clock domain to a second receiver located in a second clock domain. The first method includes the steps of creating a programmable delay element between the first and second receivers, and selectively adding delay via the programmable delay element to the signals until the signals are aligned. Numerous other aspects are provided.
摘要翻译：在本发明的第一方面，提供了一种第一种方法，用于将来自位于第一时钟域中的第一接收机的信号对准位于第二时钟域中的第二接收机。第一种方法包括以下步骤：在第一和第二接收机之间创建可编程延迟元件，并且经由可编程延迟元件选择性地将延迟添加到信号中直到信号被对准。提供了许多其他方面。

19. 发明授权

US06321312B1 System and method for controlling peripheral device memory access in a data processing system 失效
标题翻译：用于在数据处理系统中控制外围设备存储器访问的系统和方法
公开(公告)号：US06321312B1
公开(公告)日：2001-11-20
申请号：US09108896
申请日：1998-07-01
申请人： Gordon Taylor Davis , Llewellyn Bradley Marshall, IV , Clarence Rosser Ogilvie , Paul Colvin Stabler
发明人： Gordon Taylor Davis , Llewellyn Bradley Marshall, IV , Clarence Rosser Ogilvie , Paul Colvin Stabler
IPC分类号： G06F1200
CPC分类号： G06F13/38
摘要： A cache based processing system is provided with a loop detection circuit for detecting the entry into and termination of program loops and for enabling peripheral device access to the main memory after completion of the first pass through the loop and terminating access when the program leaves the loop.
摘要翻译：基于缓存的处理系统设置有环路检测电路，用于检测程序循环的进入和终止，并且用于在完成第一次循环之后使外围设备能够访问主存储器，并且当程序离开循环时终止访问。

20. 发明授权

US07536496B2 Method and apparatus for transmitting data in an integrated circuit 失效
标题翻译：用于在集成电路中传输数据的方法和装置
公开(公告)号：US07536496B2
公开(公告)日：2009-05-19
申请号：US11276449
申请日：2006-02-28
申请人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
发明人： W. Riyon Harding , David W. Milton , Clarence Rosser Ogilvie , Jason E. Rotella , Paul M. Schanely , Sebastian T. Ventrone
IPC分类号： G06F13/00 , G06F13/42 , G06F13/362 , H04L12/28 , H04L12/56 , H03K17/00
CPC分类号： G06F13/14 , G06F13/362
摘要： A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.
摘要翻译：一种用于在驻留在集成电路中的核之间传送数据的方法和装置。通过使用位于核心和仲裁器之间的集线器来传输数据。仲裁器维护一个表，其中包含核心之间路由路径的所有有效组合。

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