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11. 发明授权

US3933735A 4-Piperidone derivatives, their preparation and their use as stabilizers 失效
标题翻译： 4-哌啶酮衍生物，它们的制备及其作为稳定剂的用途
公开(公告)号：US3933735A
公开(公告)日：1976-01-20
申请号：US470309
申请日：1974-05-15
申请人： Keisuke Murayama , Susumu Higashida , Katsuaki Matsui , Tomoyuki Kurumada , Noriyuki Ohta , Hisayu Ohsawa
发明人： Keisuke Murayama , Susumu Higashida , Katsuaki Matsui , Tomoyuki Kurumada , Noriyuki Ohta , Hisayu Ohsawa
IPC分类号： C08K5/3435 , C08K5/00
CPC分类号： C08K5/3435
摘要： 4-Piperidone derivatives having the formulae ##SPC1##Wherein R represents a phenyl or naphthyl group which may be substituted with nitro, lower alkyl, halogen, hydroxyl, lower alkyl hydroxy, hydroxy lower alkyl or formyl or a 5- or 6-membered heterocyclic group having as a hetero atom at least one of oxygen atom, sulfur atom and nitrogen atom and R.sub.1 represents hydrogen atom or an alkyl group of 1 to 4 carbon atoms. They are useful as stabilizers for various synthetic polymers against their photo- and thermal-deteriorations and the 4-piperidone derivatives (II) are prepared from the corresponding 2,2,6,6-tetramethyl-4-oxopiperidine derivatives by reaction with an aldehyde and the 4-piperidone derivatives (I) are prepared from the 4-piperidone derivatives (II) through dehydration.
摘要翻译：具有下式的4-哌啶酮衍生物，其中R表示可被硝基，低级烷基，卤素，羟基，低级烷基羟基，羟基低级烷基或甲酰基取代的苯基或萘基或具有如下基团的5-或6-元杂环基氧原子，硫原子和氮原子中的至少一个为杂原子，R 1表示氢原子或碳原子数1〜4的烷基。它们可用作各种合成聚合物对其光热和热变质的稳定剂，4-哌啶酮衍生物（II）由相应的2,2,6,6-四甲基-4-氧代哌啶衍生物与醛反应制备通过脱水由4-哌啶酮衍生物（II）制备4-哌啶酮衍生物（I）。

12. 发明授权

US07484135B2 Semiconductor device having a mode of functional test 失效
标题翻译：具有功能测试模式的半导体器件
公开(公告)号：US07484135B2
公开(公告)日：2009-01-27
申请号：US11374076
申请日：2006-03-14
申请人： Katsuaki Matsui
发明人： Katsuaki Matsui
IPC分类号： G06K5/04
CPC分类号： G11C29/02 , G11C29/025 , G11C29/50012
摘要： A semiconductor device includes a circuit block; a first signal path for guiding a test signal to a signal input terminal of the circuit block; a second signal path for guiding a test clock to a clock input terminal of the circuit block; a third signal path for guiding a test output signal from a output terminal of the circuit block to a pad via a dummy latch; and a fourth signal path for guiding the test output signal from the output terminal of the circuit block, to another pad. A dummy latch latches the test output signal at substantially a same speed as an operational latch during a normal operation. The third signal path has a wiring delay time from the output terminal to the dummy latch that is substantially equal to a wiring delay time from the output terminal to the operational latch.
摘要翻译：半导体器件包括电路块; 用于将测试信号引导到电路块的信号输入端的第一信号路径; 用于将测试时钟引导到电路块的时钟输入端的第二信号路径; 第三信号路径，用于经由虚拟锁存器将测试输出信号从电路块的输出端引导到焊盘; 以及用于将测试输出信号从电路块的输出端引导到另一个焊盘的第四信号路径。在正常操作期间，虚拟闩锁以与操作闩锁基本相同的速度锁存测试输出信号。第三信号路径具有从输出端子到虚拟锁存器的布线延迟时间，其基本上等于从输出端子到操作锁存器的布线延迟时间。

13. 发明授权

US07092302B2 Nonvolatile semiconductor memory device 有权
公开(公告)号：US07092302B2
公开(公告)日：2006-08-15
申请号：US11144767
申请日：2005-06-06
申请人： Katsuaki Matsui
发明人： Katsuaki Matsui
IPC分类号： G11C13/00
CPC分类号： G11C29/82 , G11C29/84
摘要： The present invention provides a nonvolatile semiconductor memory device capable of achieving the speeding-up of reading and a reduction in layout area. A control gate electrode of each of memory cell transistors employed in the nonvolatile semiconductor memory device according to the present invention is configured so as to be capable of assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential upon its operation. A second NMOS transistor is provided between the gate of a first NMOS transistor that drives a control gate electrode (WL) to the first power supply potential (VCC) and a control signal (/ER) connected to the gate thereof. The source of the second NMOS transistor is inputted with the control signal (/ER) and the drain thereof is connected to the gate of the first NMOS transistor. A PMOS transistor is provided in parallel with the first NMOS transistor. A transfer gate comprising these NMOS and PMOS transistors drives the control gate electrode (WL).

14. 发明授权

US06975164B1 Method and device for generating constant voltage 失效
标题翻译：用于产生恒定电压的方法和装置
公开(公告)号：US06975164B1
公开(公告)日：2005-12-13
申请号：US09014401
申请日：1998-01-27
申请人： Katsuaki Matsui , Yoshimasa Sekino
发明人： Katsuaki Matsui , Yoshimasa Sekino
IPC分类号： G05F1/56 , G05F1/10 , G05F1/565 , G11C5/14 , G11C11/4074 , G11C11/4099
CPC分类号： G05F1/565 , G11C5/147 , G11C11/4074 , G11C11/4099
摘要： In order to generate a constant voltage, a reference voltage is generated. Short wave noises are cut off from the reference voltage. A control signal is generated based on the reference voltage and an output voltage. The output voltage is controlled in response to the control signal to provide a constant output voltage.
摘要翻译：为了产生恒定电压，产生参考电压。短波噪声与参考电压相切。基于参考电压和输出电压产生控制信号。响应于控制信号控制输出电压以提供恒定的输出电压。

15. 发明授权

US5768210A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5768210A
公开(公告)日：1998-06-16
申请号：US833045
申请日：1997-04-03
申请人： Katsuaki Matsui , Tamihiro Ishimura
发明人： Katsuaki Matsui , Tamihiro Ishimura
IPC分类号： G11C11/41 , G11C7/10 , G11C11/401 , G11C11/409 , G11C11/4096 , G11C11/419 , G11C7/00
CPC分类号： G11C11/419 , G11C11/4096 , G11C7/1048
摘要： A semiconductor memory device according to the present invention comprise a plurality of arrays each supplied with a common column address signal. In an selected array, the potential of a data line is set to a potential corresponding to a potential supplied to a corresponding bit line in response to the potential of the bit line, the potential of the corresponding column address signal and the potential of a terminal. In non-selected array other than the selected array at this time, since the potential of a terminal in the non-selected array is set to a potential different from that of the terminal in the selected array, the potential of the data line remains unchanged irrespective of the column address signal.
摘要翻译：根据本发明的半导体存储器件包括多个阵列，每个阵列都具有公共列地址信号。在所选择的阵列中，响应于位线的电位，相应的列地址信号的电位和端子的电位，将数据线的电位设置为对应于提供给相应位线的电位的电位。在这个时候，除了所选择的阵列以外的非选择的阵列中，由于未选择的阵列中的终端的电位被设置为与所选阵列中的终端的电位不同的电位，所以数据线的电位保持不变不管列地址信号如何。

16. 发明申请

US20120230133A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND DATA WRITING METHOD 有权
标题翻译：非易失性半导体存储器件和数据写入方法
公开(公告)号：US20120230133A1
公开(公告)日：2012-09-13
申请号：US13413335
申请日：2012-03-06
申请人： Katsuaki Matsui , Junya Ogawa
发明人： Katsuaki Matsui , Junya Ogawa
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C16/0475
摘要： A nonvolatile semiconductor memory quickly and precisely accumulates a desired amount of charges corresponding to data-to-be-written in a charge accumulating part of a memory cell. When charges are injected into the charge accumulating part of the memory cell by applying a writing voltage corresponding to the data-to-be-written to the drain or source region of the memory cell, the writing voltage is reduced on the basis of an increase in the amount of charges accumulated in the charge accumulating part.
摘要翻译：非易失性半导体存储器快速且精确地累积与要写入存储单元的电荷累积部分中的数据相对应的期望量的电荷。当通过向存储单元的漏极或源极区域施加与要写入的数据相对应的写入电压将电荷注入存储单元的电荷累积部分时，基于增加的写入电压减小在电荷累积部分积累的电荷量。

17. 发明授权

US07808835B2 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07808835B2
公开(公告)日：2010-10-05
申请号：US12408896
申请日：2009-03-23
申请人： Hirokazu Miyazaki , Katsuaki Matsui , Tsutomu Higuchi
发明人： Hirokazu Miyazaki , Katsuaki Matsui , Tsutomu Higuchi
IPC分类号： G11C11/34
CPC分类号： G11C7/067 , G11C7/08 , G11C16/0441 , G11C16/26
摘要： In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.
摘要翻译：在由闪速存储器构成的存储单元阵列中，多个提供了一对具有相互相反值的数据被写入的正存储单元和负存储单元。连接到数据读取对象的存储单元的位线和I / O线被充电，然后提高连接到数据读取对象存储单元的字线的电位WL。因此，根据写入的数据，电流在数据读取对象存储单元中流动，因此I / O线的电位BL和电位BLN之一开始下降。当电位BL和BLN中的一个低于读出放大器的电路阈值时，建立读取数据，并将所建立的读取数据作为读出放大器输出信号SAOUT输出。

18. 发明申请

US20080025110A1 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20080025110A1
公开(公告)日：2008-01-31
申请号：US11785527
申请日：2007-04-18
申请人： Hirokazu Miyazaki , Katsuaki Matsui , Tsutomu Higuchi
发明人： Hirokazu Miyazaki , Katsuaki Matsui , Tsutomu Higuchi
IPC分类号： G11C7/06
CPC分类号： G11C7/067 , G11C7/08 , G11C16/0441 , G11C16/26
摘要： In a memory cell array which is constituted with flash memory, a pair of a positive memory cell and a negative memory cell, to which data with mutually opposite values are written, is plurally provided. Bit lines and I/O lines connected to the memory cells of a data reading object are charged, and then a potential WL of a word line connected to the data reading object memory cells is raised. Hence, currents flow in the data reading object memory cells in accordance with the data that were written, and consequently one of a potential BL and a potential BLN of the I/O lines begins to fall. When one of the potentials BL and BLN falls below the circuit threshold of a sense amplifier, reading data is established, and the established reading data is outputted as a sense amplifier output signal SAOUT.
摘要翻译：在由闪速存储器构成的存储单元阵列中，多个提供了一对具有相互相反值的数据被写入的正存储单元和负存储单元。连接到数据读取对象的存储单元的位线和I / O线被充电，然后提高连接到数据读取对象存储单元的字线的电位WL。因此，根据写入的数据，电流在数据读取对象存储单元中流动，因此I / O线的电位BL和电位BLN之一开始下降。当电位BL和BLN中的一个低于读出放大器的电路阈值时，建立读取数据，并将所建立的读取数据作为读出放大器输出信号SAOUT输出。

19. 发明授权

US06977861B1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06977861B1
公开(公告)日：2005-12-20
申请号：US10911515
申请日：2004-08-05
申请人： Katsuaki Matsui
发明人： Katsuaki Matsui
IPC分类号： G11C8/00 , G11C29/00
CPC分类号： G11C29/82 , G11C29/84
摘要： The present invention provides a nonvolatile semiconductor memory device capable of achieving the speeding-up of reading and a reduction in layout area. A control gate electrode of each of memory cell transistors employed in the nonvolatile semiconductor memory device according to the present invention is configured so as to be capable of assuming a first power supply potential (VCC) and a second power supply potential (VPP) higher than the first power supply potential upon its operation. A second NMOS transistor is provided between the gate of a first NMOS transistor that drives a control gate electrode (WL) to the first power supply potential (VCC) and a control signal (/ER) connected to the gate thereof. The source of the second NMOS transistor is inputted with the control signal (/ER) and the drain thereof is connected to the gate of the first NMOS transistor. A PMOS transistor is provided in parallel with the first NMOS transistor. A transfer gate comprising these NMOS and PMOS transistors drives the control gate electrode (WL).
摘要翻译：本发明提供一种能够实现读取加速和布局面积减小的非易失性半导体存储器件。在根据本发明的非易失性半导体存储器件中使用的每个存储单元晶体管的控制栅电极被配置为能够使第一电源电位（VCC）和第二电源电位（VPP）高于其运行时的第一个电源潜力。第二NMOS晶体管设置在驱动控制栅电极（WL）到第一电源电位（VCC）的第一NMOS晶体管的栅极和连接到其栅极的控制信号（/ ER）之间。第二NMOS晶体管的源极输入控制信号（/ ER），其漏极连接到第一NMOS晶体管的栅极。 PMOS晶体管与第一NMOS晶体管并联提供。包括这些NMOS和PMOS晶体管的传输门驱动控制栅电极（WL）。

20. 发明授权

US06774708B2 Voltage boosting circuit with two main charge pumps 有权
标题翻译：两个主电荷泵的升压电路
公开(公告)号：US06774708B2
公开(公告)日：2004-08-10
申请号：US10218078
申请日：2002-08-14
申请人： Katsuaki Matsui
发明人： Katsuaki Matsui
IPC分类号： G05F302
CPC分类号： H02M3/07 , H02M2003/077
摘要： A voltage boosting circuit has two charge pumps connected to an output node from which a boosted potential, higher than the power-supply potential, is supplied to a load circuit. One charge pump is activated when the load circuit is activated, regardless of the output node potential. The other charge pump is activated while the load circuit is active, if the potential of the output node falls below a predetermined level. Use of these two charge pumps reduces electrical noise and ensures that the output node is brought to an adequate potential when the load circuit is activated.
摘要翻译：升压电路具有连接到输出节点的两个电荷泵，高于电源电位的升压电势被提供给负载电路。负载电路激活时，无论输出节点电位如何，都会激活一个电荷泵。如果输出节点的电位低于预定电平，则另一个电荷泵在负载电路有效时被激活。使用这两个电荷泵可以降低电气噪声，并确保在负载电路被激活时使输出节点达到足够的电位。

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