专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US07054187B2 Magnetic memory 有权
公开(公告)号：US07054187B2
公开(公告)日：2006-05-30
申请号：US10981508
申请日：2004-11-05
申请人： Tatsuya Kishi , Minoru Amano , Yoshiaki Saito , Shigeki Takahashi , Katsuya Nishiyama , Yoshiaki Asao , Hiroaki Yoda , Tomomasa Ueda , Yoshihisa Iwata
发明人： Tatsuya Kishi , Minoru Amano , Yoshiaki Saito , Shigeki Takahashi , Katsuya Nishiyama , Yoshiaki Asao , Hiroaki Yoda , Tomomasa Ueda , Yoshihisa Iwata
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetic memory includes: a magnetoresistance effect element having a magnetic recording layer; a first writing wiring extending in a first direction on or below the magnetoresistance effect element, a center of gravity of an axial cross section of the wiring being apart from a center of thickness at the center of gravity, and the center of gravity being eccentric toward the magnetoresistance effect element; and a writing circuit configured to pass a current through the first writing wiring in order to record an information in the magnetic recording layer by a magnetic field generated by the current.

12. 发明授权

US08111538B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08111538B2
公开(公告)日：2012-02-07
申请号：US12273874
申请日：2008-11-19
申请人： Keiji Hosotani , Yoshiaki Asao , Yoshihisa Iwata
发明人： Keiji Hosotani , Yoshiaki Asao , Yoshihisa Iwata
IPC分类号： G11C11/00
CPC分类号： G11C7/20 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C29/028 , G11C29/50 , G11C2013/0083 , G11C2029/1206 , G11C2029/5002 , G11C2213/31 , G11C2213/32 , G11C2213/79
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data. An allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched when a power source is turned on.
摘要翻译：半导体存储器件包括具有根据“0”数据/“1”数据被设置成低电阻状态/高电阻状态的多个存储器单元的存储单元阵列。当电源接通时，切换“0”数据/“1”数据和低电阻状态/高电阻状态的分配。

13. 发明授权

US06795334B2 Magnetic random access memory 失效
标题翻译：磁性随机存取存储器
公开(公告)号：US06795334B2
公开(公告)日：2004-09-21
申请号：US10180024
申请日：2002-06-27
申请人： Yoshihisa Iwata , Yoshiaki Asao , Keiji Hosotani , Junichi Miyamoto
发明人： Yoshihisa Iwata , Yoshiaki Asao , Keiji Hosotani , Junichi Miyamoto
IPC分类号： G11C1100
CPC分类号： G11C11/16 , G11C11/5607
摘要： A read blocks are connected to a read bit line. The read block has MTJ elements connected in series or in parallel, or arranged by combining series and parallel connections between the read bit line and a ground terminal. The MTJ elements are stacked on a semiconductor substrate. The read bit line is arranged on the MTJ elements stacked. A write word line extending in the X-direction and a write bit line extending in the Y-direction are present near the MTJ elements in the read block.
摘要翻译：一个读块连接到读位线。读块具有串联或并联连接的MTJ元件，或通过组合读位线与接地端之间的串联和并联连接进行排列。 MTJ元件堆叠在半导体衬底上。读取位线被布置在堆叠的MTJ元件上。在读取块中的MTJ元素附近存在沿X方向延伸的写字线和在Y方向上延伸的写位线。

14. 发明申请

US20090129141A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20090129141A1
公开(公告)日：2009-05-21
申请号：US12273874
申请日：2008-11-19
申请人： Keiji HOSOTANI , Yoshiaki Asao , Yoshihisa Iwata
发明人： Keiji HOSOTANI , Yoshiaki Asao , Yoshihisa Iwata
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/20 , G11C11/16 , G11C13/0004 , G11C13/0007 , G11C29/028 , G11C29/50 , G11C2013/0083 , G11C2029/1206 , G11C2029/5002 , G11C2213/31 , G11C2213/32 , G11C2213/79
摘要： A semiconductor memory device includes a memory cell array having a plurality of memory cells which are set into low-resistance states/high-resistance states according to “0” data/“1” data. An allocation of the “0” data/“1” data and the low-resistance state/high-resistance state is switched when a power source is turned on.
摘要翻译：半导体存储器件包括具有根据“0”数据/“1”数据被设置成低电阻状态/高电阻状态的多个存储器单元的存储单元阵列。当电源接通时，切换“0”数据/“1”数据和低电阻状态/高电阻状态的分配。

15. 发明授权

US07376003B2 Magnetic random access memory 有权
标题翻译：磁性随机存取存储器
公开(公告)号：US07376003B2
公开(公告)日：2008-05-20
申请号：US10465616
申请日：2003-06-20
申请人： Yoshihisa Iwata , Yoshiaki Asao , Kentaro Nakajima
发明人： Yoshihisa Iwata , Yoshiaki Asao , Kentaro Nakajima
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetic field H1 in the hard-axis direction and a magnetic field H2 in the easy-axis direction are caused to simultaneously act on a MTJ element having an ideal asteroid curve, thereby reversing the magnetizing direction of the storing layer of the MTJ element. When the actual asteroid curve shifts in the hard-axis direction by Ho, a corrected synthesized magnetic field ({right arrow over (H1)}+{right arrow over (H2)}+{right arrow over (Ho)}) is generated in write operation to reliably reverse the magnetizing direction. The corrected synthesized magnetic field can easily be generated by individually controlling a write word/bit line current on the basis of programmed setting data.
摘要翻译：使硬轴方向的磁场H 1和易轴方向的磁场H 2同时作用于具有理想的小行星曲线的MTJ元件，从而使MTJ的存储层的磁化方向反转元件。当实际的小行星曲线在硬轴方向上移动Ho时，产生校正的合成磁场（{H 1}} + {右箭头（H 2）} +（向右箭头（Ho））上的右箭头在写入操作中可靠地反转磁化方向，通过基于编程的设置数据单独地控制写入字/位线电流，可以容易地产生校正的合成磁场。

16. 发明申请

US20050141262A1 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US20050141262A1
公开(公告)日：2005-06-30
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： H01L27/108 , G11C11/24 , G11C11/404 , H01L21/8239 , H01L21/8242 , H01L21/84 , H01L27/105 , H01L27/12
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

17. 发明授权

US07075820B2 Semiconductor memory device for dynamically storing data with channel body of transistor used as storage node 失效
标题翻译：半导体存储器件，用于动态存储与用作存储节点的晶体管通道体的数据
公开(公告)号：US07075820B2
公开(公告)日：2006-07-11
申请号：US10845403
申请日：2004-05-14
申请人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
发明人： Takashi Yamada , Fumio Horiguchi , Takashi Ohsawa , Yoshihisa Iwata , Yoshiaki Asao
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： H01L27/108 , H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/7841 , H01L29/785
摘要： A semiconductor memory device includes a plurality of MIS transistors arranged at intersections of first word lines and bit lines formed on an SOI substrate and each configuring a memory cell. Each of the plurality of MIS transistors includes a channel body formed in a semiconductor layer on an insulating film and set in an electrically floating state, a first extension region formed in contact with the channel body in the semiconductor layer and arranged in a first word line direction, a gate insulating film formed on the channel body, a gate electrode formed on the gate insulating film and electrically connected to a corresponding one of the first word lines, and source and drain regions separately formed in a bit line direction in the semiconductor layer to sandwich the channel body.
摘要翻译：半导体存储器件包括多个MIS晶体管，其布置在形成在SOI衬底上的第一字线和位线的交点处，并且每个配置存储器单元。多个MIS晶体管中的每一个包括形成在绝缘膜上的半导体层中并设置为电浮置状态的沟道体，与半导体层中的沟道体接触形成并布置在第一字线中的第一延伸区域形成在沟道体上的栅极绝缘膜，形成在栅极绝缘膜上并电连接到第一字线中的相应一个的栅极电极以及在半导体层中分别形成在位线方向上的源极和漏极区域夹住通道体。

18. 发明申请

US20050195673A1 Magnetic random access memory having memory cells configured by use of tunneling magnetoresistive elements 审中-公开
标题翻译：具有通过使用隧道磁阻元件配置存储单元的磁性随机存取存储器
公开(公告)号：US20050195673A1
公开(公告)日：2005-09-08
申请号：US10617666
申请日：2003-07-14
申请人： Yoshiaki Asao , Yoshihisa Iwata
发明人： Yoshiaki Asao , Yoshihisa Iwata
IPC分类号： G11C7/00
CPC分类号： G11C11/1673 , G11C11/1659 , G11C11/1675
摘要： A magnetic random access memory includes memory cells each including a TMR element and a selection element, and a read circuit which reads storage information from the TMR element by applying read voltage to a selected one of the memory cells and causing a current to flow through the TMR element via the selection element. The read circuit includes a voltage setting section used to apply voltage which makes a resistance variation rate of the TMR element substantially equal to half a resistance variation rate thereof obtained when 0 V is applied across the TMR element to the TMR element at the information read time.
摘要翻译：磁性随机存取存储器包括各自包括TMR元件和选择元件的存储单元，以及读取电路，其通过将读取电压施加到所选择的一个存储器单元并且使电流流过所述存储器单元而从TMR元件读取存储信息 TMR元素通过选择元素。读取电路包括用于施加电压的电压设定部分，其使TMR元件的电阻变化率基本上等于当在信息读取时间TMR元件向TMR元件施加0V时获得的电阻变化率的一半。

19. 发明授权

US06950334B2 Magnetic random access memory having test circuit and test method therefor 失效
标题翻译：具有测试电路的磁性随机存取存储器及其测试方法
公开(公告)号：US06950334B2
公开(公告)日：2005-09-27
申请号：US10728917
申请日：2003-12-08
申请人： Yuui Shimizu , Yoshihisa Iwata , Kenji Tsuchida , Tatsuya Kishi
发明人： Yuui Shimizu , Yoshihisa Iwata , Kenji Tsuchida , Tatsuya Kishi
IPC分类号： G01R31/28 , G11C11/15 , G11C29/04 , G11C29/12 , G11C11/14 , G11C29/00
CPC分类号： G11C11/16 , G11C29/12
摘要： An MRAM has an internal test circuit. This test circuit detects a bit in a memory cell array, which has a shift in write characteristics, as a defective bit by using a method of applying a one-axis write current along an axis of hard magnetization.
摘要翻译： MRAM具有内部测试电路。该测试电路通过使用沿着硬磁化轴施加单轴写入电流的方法来检测具有写特性偏移的存储单元阵列中的位作为有缺陷位。

20. 发明申请

US20050047202A1 Magnetic random access memory having test circuit and test method therefor 失效
公开(公告)号：US20050047202A1
公开(公告)日：2005-03-03
申请号：US10728917
申请日：2003-12-08
申请人： Yuui Shimizu , Yoshihisa Iwata , Kenji Tsuchida , Tatsuya Kishi
发明人： Yuui Shimizu , Yoshihisa Iwata , Kenji Tsuchida , Tatsuya Kishi
IPC分类号： G01R31/28 , G11C11/15 , G11C29/04 , G11C29/12 , G11C11/00
CPC分类号： G11C11/16 , G11C29/12
摘要： An MRAM has an internal test circuit. This test circuit detects a bit in a memory cell array, which has a shift in write characteristics, as a defective bit by using a method of applying a one-axis write current along an axis of hard magnetization.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式