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11. 发明授权

US09012975B2 Field effect transistor and manufacturing method thereof 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US09012975B2
公开(公告)日：2015-04-21
申请号：US13517759
申请日：2012-06-14
申请人： Tong-Yu Chen , Chih-Jung Wang
发明人： Tong-Yu Chen , Chih-Jung Wang
IPC分类号： H01L29/792 , H01L29/66 , H01L29/78 , H01L21/28 , H01L29/423
CPC分类号： H01L29/66833 , H01L21/28282 , H01L21/31111 , H01L21/31144 , H01L29/42344 , H01L29/66795 , H01L29/785 , H01L29/792
摘要： A field effect transistor (FET) and a manufacturing method thereof are provided. The FET includes a substrate, a fin bump, an insulating layer, a charge trapping structure and a gate structure. The fin bump is disposed on the substrate. The insulating layer is disposed on the substrate and located at two sides of the fin bump. The charge trapping structure is disposed on the insulating layer and located at at least one side of the fin bump. A cross-section of the charge trapping structure is L-shaped. The gate structure covers the fin bump and the charge trapping structure.
摘要翻译：提供场效应晶体管（FET）及其制造方法。 FET包括衬底，鳍片凸块，绝缘层，电荷俘获结构和栅极结构。翅片凸块设置在基板上。绝缘层设置在基板上并且位于散热片凸块的两侧。电荷捕获结构设置在绝缘层上并位于散热片凸块的至少一侧。电荷捕获结构的横截面为L形。栅极结构覆盖鳍片凸起和电荷俘获结构。

12. 发明授权

US08946078B2 Method of forming trench in semiconductor substrate 有权
标题翻译：在半导体衬底中形成沟槽的方法
公开(公告)号：US08946078B2
公开(公告)日：2015-02-03
申请号：US13426624
申请日：2012-03-22
申请人： Tong-Yu Chen , Chih-Jung Wang
发明人： Tong-Yu Chen , Chih-Jung Wang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/0337 , H01L21/0338 , H01L21/28132 , H01L21/3086 , H01L21/3088 , H01L21/311 , H01L21/31111 , H01L21/31116 , H01L21/31133 , H01L21/31138 , H01L21/31144 , H01L29/66795
摘要： The present invention provides a method of forming a trench in a semiconductor substrate. First, a first patterned mask layer is formed on a semiconductor substrate. The first patterned mask layer has a first trench. Then, a material layer is formed along the first trench. Then, a second patterned mask layer is formed on the material layer to completely fill the first trench. A part of the material layer is removed when the portion of the material layer between the second patterned mask layer and the semiconductor substrate is maintained so as to form a second trench. Lastly, an etching process is performed by using the first patterned mask layer and the second patterned mask layer as a mask.
摘要翻译：本发明提供一种在半导体衬底中形成沟槽的方法。首先，在半导体衬底上形成第一图案化掩模层。第一图案化掩模层具有第一沟槽。然后，沿着第一沟槽形成材料层。然后，在材料层上形成第二图案化掩模层以完全填充第一沟槽。当保持第二图案化掩模层和半导体衬底之间的材料层的部分以形成第二沟槽时，去除材料层的一部分。最后，通过使用第一图案化掩模层和第二图案化掩模层作为掩模来执行蚀刻工艺。

13. 发明授权

US06361929B1 Method of removing a photo-resist layer on a semiconductor wafer 有权
标题翻译：去除半导体晶片上的光致抗蚀剂层的方法
公开(公告)号：US06361929B1
公开(公告)日：2002-03-26
申请号：US09373755
申请日：1999-08-13
申请人： Hsein-Ta Chung , Yi-Yu Hsu , Tong-Yu Chen , Tri-Rung Yew
发明人： Hsein-Ta Chung , Yi-Yu Hsu , Tong-Yu Chen , Tri-Rung Yew
IPC分类号： G03F736
CPC分类号： G03F7/427 , G03F7/42
摘要： The present invention relates to a method of removing a photo-resist layer from a semiconductor wafer. The semiconductor wafer comprises an inter-metal dielectric layer (IMD), and a photo-resist layer positioned on the IMD. The method comprises performing a dry cleaning process by injecting a nitrogen-containing gas into an oxygen-free environment and utilizing a plasma reaction to remove most of the photo-resist layer, and performing a wet cleaning process to completely remove the photo-resist layer.
摘要翻译：本发明涉及从半导体晶片去除光致抗蚀剂层的方法。半导体晶片包括金属间介电层（IMD）和位于IMD上的光致抗蚀剂层。该方法包括通过将含氮气体注入无氧环境并利用等离子体反应去除大部分光致抗蚀剂层进行干洗处理，并进行湿式清洗处理以完全除去光致抗蚀剂层。

14. 发明授权

US6083845A Etching method 有权
标题翻译：蚀刻方法
公开(公告)号：US6083845A
公开(公告)日：2000-07-04
申请号：US255678
申请日：1999-02-23
申请人： Chan-Lon Yang , Tong-Yu Chen
发明人： Chan-Lon Yang , Tong-Yu Chen
IPC分类号： H01L21/311 , H01L21/60 , H01L21/768 , H01L21/00
CPC分类号： H01L21/76897 , H01L21/31116 , H01L21/76816
摘要： An etching method used in the high density plasma etching system to etch a silicon oxide dielectric layer to form openings of different depths. The method uses a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, and Ar as an etching gas source to etch the silicon oxide dielectric layer, forming a plurality of openings of a first depth. A mixture of C.sub.4 H.sub.8, CO, and Ar is used as an etching gas source to etch the silicon oxide dielectric layer exposed by the first opening, so that the opening is deepened to the second depth. Using a mixture of C.sub.4 H.sub.8, CH.sub.2 F.sub.2, CO, and Ar as the etching gas source, the silicon oxide dielectric layer exposed by the opening is etched, so that the openings are deepened to the third depth and the fourth depth.
摘要翻译：在高密度等离子体蚀刻系统中使用蚀刻方法来蚀刻氧化硅介电层以形成不同深度的开口。该方法使用C4H8，CH2F2和Ar的混合物作为蚀刻气体源来蚀刻氧化硅介电层，形成第一深度的多个开口。使用C4H8，CO和Ar的混合物作为蚀刻气体源来蚀刻由第一开口暴露的氧化硅介电层，使得开口加深到第二深度。使用C4H8，CH2F2，CO和Ar的混合物作为蚀刻气体源，蚀刻由开口暴露的氧化硅介电层，使得开口加深到第三深度和第四深度。

15. 发明申请

US20130234301A1 PATTERNED STRUCTURE OF SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF 有权
标题翻译：半导体器件的图形结构及其制作方法
公开(公告)号：US20130234301A1
公开(公告)日：2013-09-12
申请号：US13417299
申请日：2012-03-11
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L29/02 , H01L21/32
CPC分类号： H01L27/11 , H01L21/0337 , H01L21/0338 , H01L21/28123 , H01L21/3213 , H01L21/823431 , H01L21/845
摘要： A method for fabricating a patterned structure in a semiconductor device is provided. First, a substrate with a first region and a second region is provided. Then, a plurality of sacrificial patterns is respectively formed within the first region and the second region. A first spacer is then formed on the sidewalls of each of the sacrificial patterns followed by forming a mask layer to cover the sacrificial patterns located within the first region. Finally, the first spacer exposed from the mask layer is trimmed to be a second spacer and the mask layer is then removed.
摘要翻译：提供了一种在半导体器件中制造图案化结构的方法。首先，提供具有第一区域和第二区域的基板。然后，分别在第一区域和第二区域内形成多个牺牲图案。然后在每个牺牲图案的侧壁上形成第一间隔物，随后形成掩模层以覆盖位于第一区域内的牺牲图案。最后，将从掩模层露出的第一间隔物修剪成第二间隔物，然后除去掩模层。

16. 发明申请

US20130175621A1 FINFET STRUCTURE AND METHOD FOR MAKING THE SAME 有权
标题翻译： FINFET结构及其制造方法
公开(公告)号：US20130175621A1
公开(公告)日：2013-07-11
申请号：US13347707
申请日：2012-01-11
申请人： Tong-Yu Chen , Chih-Jung Wang
发明人： Tong-Yu Chen , Chih-Jung Wang
IPC分类号： H01L29/78 , H01L21/336 , H01L29/786
CPC分类号： H01L29/785 , H01L29/66787 , H01L29/7843
摘要： A finFET device includes a substrate, at least a first fin structure disposed on the substrate, a L-shaped insulator surrounding the first fin structure and exposing, at least partially, the sidewalls of the first fin structure, wherein the height of the L-shaped insulator is inferior to the height of the first fin structure in order to expose parts of the sidewalls surface of the first fin structure, and a gate structure disposed partially on the L-shaped insulator and partially on the first fin structure.
摘要翻译： finFET器件包括衬底，至少设置在衬底上的第一鳍结构，围绕第一鳍结构并且至少部分地暴露第一鳍结构的侧壁的L形绝缘体，其中，为了露出第一鳍片结构的侧壁表面的部分，以及部分地设置在L形绝缘体上并部分地设置在第一鳍片结构上的栅极结构，第一翅片结构的高度劣于第一翅片结构的高度。

17. 发明申请

US20130105867A1 Method of fabricating field effect transistor with fin structure and field effect transistor with fin structure fabricated therefrom 有权
标题翻译：具有翅片结构的场效应晶体管和由其制造的鳍结构的场效应晶体管的方法
公开(公告)号：US20130105867A1
公开(公告)日：2013-05-02
申请号：US13284987
申请日：2011-10-31
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/7851 , H01L29/0649 , H01L29/66545 , H01L29/66818
摘要： A method of fabricating a field effect transistor with a fin structure is described. At least a fin structure is formed on a substrate. A planar insulation layer covering the fin structure is formed. A trench is formed in the insulation layer and intersects the fin structure both lengthwise, and thereby an upper portion of the fin structure is exposed to the trench. The exposed upper portion of the fin structure will serve as a gate channel region. A gate structure covering the upper portion is formed within the trench. The upper portion of the fin structure may be further trimmed. Accordingly, the present invention also relates to a field effect transistor with a fin structure, in which, the channel width is less than the source/drain width, and a gate structure has two sidewalls contacting two opposite sidewalls of a source region and a drain region, respectively.
摘要翻译：描述了制造具有翅片结构的场效应晶体管的方法。至少在基板上形成翅片结构。形成覆盖翅片结构的平面绝缘层。在绝缘层中形成沟槽，并且纵向地与鳍状结构相交，从而翅片结构的上部暴露于沟槽。鳍结构的暴露的上部将用作栅极沟道区。在沟槽内形成覆盖上部的栅极结构。翅片结构的上部可以进一步修整。因此，本发明还涉及具有翅片结构的场效应晶体管，其中沟道宽度小于源极/漏极宽度，并且栅极结构具有接触源极区域和漏极的两个相对侧壁的两个侧壁区域。

18. 发明申请

US20130037918A1 Semiconductor Structure and Manufacturing Method Thereof 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130037918A1
公开(公告)日：2013-02-14
申请号：US13206523
申请日：2011-08-10
申请人： Tong-Yu Chen
发明人： Tong-Yu Chen
IPC分类号： H01L29/06 , H01L21/311
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/76816 , H01L21/76838
摘要： A semiconductor structure is provided in the present invention. The semiconductor structure includes a substrate, a first material layer and a second material layer. A trench region is defined on the substrate. The trench region includes two separated first regions and a second region, wherein the second region is adjacent to and between the two first regions. The first material layer is disposed on the substrate outside the trench region. The second material layer is disposed in the second region and is level with the first material layer.
摘要翻译：在本发明中提供半导体结构。半导体结构包括基板，第一材料层和第二材料层。在衬底上限定沟槽区域。沟槽区域包括两个分开的第一区域和第二区域，其中第二区域与两个第一区域相邻并且在两个第一区域之间。第一材料层设置在沟槽区域外的衬底上。第二材料层设置在第二区域中并与第一材料层平齐。

19. 发明申请

US20050110152A1 Method for forming openings in low dielectric constant material layer 审中-公开
标题翻译：低介电常数材料层开口形成方法
公开(公告)号：US20050110152A1
公开(公告)日：2005-05-26
申请号：US11021411
申请日：2004-12-23
申请人： Chih-Jung Wang , Tong-Yu Chen
发明人： Chih-Jung Wang , Tong-Yu Chen
IPC分类号： H01L21/027 , H01L21/28 , H01L21/302 , H01L21/311 , H01L21/4763 , H01L21/768 , H01L29/40
CPC分类号： H01L21/76811 , H01L21/0276 , H01L21/31144 , H01L21/76813
摘要： The invention is directed towards a method for forming openings in low-k dielectric layers and a structure for forming an opening thereof. A mask layer comprising at least one metal hard mask layer and one or more hard mask layers is applied on the dielectric layer for forming the opening.
摘要翻译：本发明涉及一种用于在低k电介质层中形成开口的方法和用于形成其开口的结构。将包括至少一个金属硬掩模层和一个或多个硬掩模层的掩模层施加在用于形成开口的介电层上。

20. 发明授权

US06638871B2 Method for forming openings in low dielectric constant material layer 有权
标题翻译：低介电常数材料层开口形成方法
公开(公告)号：US06638871B2
公开(公告)日：2003-10-28
申请号：US10044322
申请日：2002-01-10
申请人： Chin-Jung Wang , Tong-Yu Chen
发明人： Chin-Jung Wang , Tong-Yu Chen
IPC分类号： H01L21311
CPC分类号： H01L21/76811 , H01L21/0276 , H01L21/31144 , H01L21/76813
摘要： The invention is directed towards a method for forming openings in low-k dielectric layers. A cap layer, a low-k dielectric layer, a metal hard mask layer and a hard mask layer are formed in sequence on a provided substrate with metal wires. After patterning the metal hard mask layer and the hard mask layer to form a first opening, a fluid filling material layer is formed on the hard mask layer and fills the first opening. Using a patterned photoresist layer as a mask to define the filling material layer and the low-k dielectric layer, a second opening is obtained. After removing the photoresist layer along with the filling material layer, a damascene opening is formed by using the metal hard mask and the hard mask layers as a mask and the cap layer as an etching stop layer.
摘要翻译：本发明涉及一种用于在低k电介质层中形成开口的方法。在金属线的所提供的基板上依次形成盖层，低k电介质层，金属硬掩模层和硬掩模层。在图案化金属硬掩模层和硬掩模层以形成第一开口之后，在硬掩模层上形成流体填充材料层并填充第一开口。使用图案化的光致抗蚀剂层作为掩模来限定填充材料层和低k电介质层，获得第二个开口。在与填充材料层一起去除光致抗蚀剂层之后，通过使用金属硬掩模和硬掩模层作为掩模和盖层作为蚀刻停止层来形成镶嵌开口。

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