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    • 15. 发明授权
    • Nonvolatile semiconductor memory device and method for manufacturing same
    • 非易失性半导体存储器件及其制造方法
    • US08786003B2
    • 2014-07-22
    • US13420722
    • 2012-03-15
    • Masao IwaseHiroyasu Tanaka
    • Masao IwaseHiroyasu Tanaka
    • H01L29/788H01L21/8247
    • H01L27/11582H01L27/0738H01L27/101H01L27/11573H01L27/11575H01L28/20
    • According to one embodiment, a nonvolatile semiconductor memory device includes: a substrate; a memory unit provided on the substrate; and a non-memory unit provided on the substrate. The memory unit includes: a first stacked body including a plurality of first electrode films and a first inter-electrode insulating film, the plurality of first electrode films being stacked along a first axis perpendicular to the major surface, the first inter-electrode insulating film being provided between two of the first electrode films mutually adjacent along the first axis; a first semiconductor layer opposing side surfaces of the first electrode films; a first memory film provided between the first semiconductor layer and the first electrode films; and a first conductive film provided on the first stacked body apart from the first stacked body. The non-memory unit includes a resistance element unit of the same layer as the conductive film.
    • 根据一个实施例,非易失性半导体存储器件包括:衬底; 设置在所述基板上的存储单元; 以及设置在基板上的非存储单元。 存储单元包括:第一层叠体,包括多个第一电极膜和第一电极间绝缘膜,所述多个第一电极膜沿着与主表面垂直的第一轴层叠,第一电极间绝缘膜 设置在沿着第一轴相互相邻的两个第一电极膜之间; 与第一电极膜的侧表面相对的第一半导体层; 设置在第一半导体层和第一电极膜之间的第一存储膜; 以及设置在与第一层叠体分离的第一层叠体上的第一导电膜。 非存储单元包括与导电膜相同层的电阻元件单元。
    • 19. 发明授权
    • Nonvolatile semiconductor memory device
    • 非易失性半导体存储器件
    • US08350326B2
    • 2013-01-08
    • US12839895
    • 2010-07-20
    • Yoshiaki FukuzumiRyota KatsumataMasaru KitoMasaru KidohHiroyasu TanakaHideaki Aochi
    • Yoshiaki FukuzumiRyota KatsumataMasaru KitoMasaru KidohHiroyasu TanakaHideaki Aochi
    • H01L29/792
    • H01L29/7926H01L21/28282H01L27/11578H01L27/11582H01L29/42344H01L29/66833
    • According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body.
    • 根据一个实施例,非易失性半导体存储器件包括第一和第二堆叠结构体,第一和第二半导体柱,存储单元连接部分,选择单元堆叠结构体,第一和第二选择单元半导体柱,选择单元连接部分 ,以及第一至第五互连。 半导体支柱刺穿堆叠的结构体。 第一和第二互连分别连接到第一和第二半导体柱。 存储单元连接部连接第一和第二半导体柱。 选择单元半导体柱刺穿选择单元堆叠结构体。 第三和第四互连分别连接到第一和第二选择单元半导体柱。 选择单元连接部分连接第一和第二选择单元半导体柱。 第五互连在与选择单元堆叠结构体相反的一侧连接到第三互连。
    • 20. 发明授权
    • Semiconductor memory device and method for manufacturing same
    • 半导体存储器件及其制造方法
    • US08338882B2
    • 2012-12-25
    • US12841662
    • 2010-07-22
    • Hiroyasu TanakaRyota KatsumataMasaru KitoYoshiaki FukuzumiHideaki Aochi
    • Hiroyasu TanakaRyota KatsumataMasaru KitoYoshiaki FukuzumiHideaki Aochi
    • H01L29/792
    • H01L27/11578H01L27/11565H01L27/11573H01L27/11575H01L27/11582
    • According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, an interconnection, and a contact plug. The base includes a substrate and a peripheral circuit formed on a surface of the substrate. The stacked body includes a plurality of conductive layers and a plurality of insulating layers alternately stacked above the base. The memory film is provided on an inner wall of a memory hole punched through the stacked body to reach a lowermost layer of the conductive layers. The memory film includes a charge storage film. The interconnection is provided below the stacked body. The interconnection electrically connects the lowermost layer of the conductive layers in an interconnection region laid out on an outside of a memory cell array region and the peripheral circuit. The contact plug pierces the stacked body in the interconnection region to reach the lowermost layer of the conductive layers in the interconnection region.
    • 根据一个实施例,半导体存储器件包括基底,堆叠体,存储膜,通道体,互连和接触插塞。 基底包括形成在基片的表面上的基片和外围电路。 堆叠体包括多个导电层和交替堆叠在基底之上的多个绝缘层。 记忆膜设置在通过层叠体冲压的存储孔的内壁上,以到达导电层的最下层。 记忆膜包括电荷存储膜。 互连设置在堆叠体的下方。 互连电连接布置在存储单元阵列区域的外部的互连区域中的导电层的最下层和外围电路。 接触插塞刺穿互连区域中的层叠体到达互连区域中的导电层的最下层。