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11. 发明授权

US5765010A Timing and control circuit and method for a synchronous vector processor 失效
标题翻译：同步矢量处理器的时序控制电路及方法
公开(公告)号：US5765010A
公开(公告)日：1998-06-09
申请号：US421471
申请日：1989-10-13
申请人： Moo-Taek Chung , Jim Childers , Hiroshi Miyaguchi , Manfred Becker
发明人： Moo-Taek Chung , Jim Childers , Hiroshi Miyaguchi , Manfred Becker
IPC分类号： F02B75/02 , G06F15/80 , H04N5/14 , H04N5/775 , H04N9/64 , H04N9/79 , G06F15/00
CPC分类号： G06F15/8092 , H04N5/775 , F02B2075/027 , H04N5/14 , H04N9/641 , H04N9/79
摘要： A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.
摘要翻译：一种用于具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置的定时和控制电路和方法。该电路包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路。

12. 发明授权

US08023359B2 System and method for converting scan data 有权
标题翻译：用于转换扫描数据的系统和方法
公开(公告)号：US08023359B2
公开(公告)日：2011-09-20
申请号：US12164680
申请日：2008-06-30
申请人： Hiroshi Miyaguchi
发明人： Hiroshi Miyaguchi
IPC分类号： G03B42/06
CPC分类号： G06T3/00
摘要： An ultrasound device generates polar-coordinate image data divided up into an (N×M) array of polar-coordinate image data blocks; a first external memory configured to store the (N×M) array of data blocks; a second external memory configured to store x-y coordinate image data corresponding to the polar-coordinate image data; a video processing chip comprising an internal memory configured to store an (N×R) array of the polar-coordinate image data blocks; and a controller configured to perform a data conversion operation on the (N×R) array of data blocks to generate x-y coordinate image data, and to store the x-y coordinate image data to the second external memory. N, M, and R are integers greater than 1; R is less than M; and an internal access time for the internal memory element is shorter than an external access time for the first external memory element.
摘要翻译：超声波装置生成被分割为（N×M）极坐标图像数据块的极坐标图像数据; 第一外部存储器，被配置为存储数据块的（N×M）个数组; 第二外部存储器，被配置为存储与所述极坐标图像数据相对应的x-y坐标图像数据; 视频处理芯片，包括被配置为存储极坐标图像数据块的（N×R）阵列的内部存储器; 以及控制器，被配置为对数据块的（N×R）阵列执行数据转换操作以生成x-y坐标图像数据，并将x-y坐标图像数据存储到第二外部存储器。 N，M和R是大于1的整数; R小于M; 并且内部存储器元件的内部访问时间比第一外部存储器元件的外部访问时间短。

13. 发明授权

US07015975B2 Image processing device with a processing unit that processes image data in units of one scan line 有权
标题翻译：具有处理单元的图像处理装置，以一条扫描线为单位处理图像数据
公开(公告)号：US07015975B2
公开(公告)日：2006-03-21
申请号：US09907312
申请日：2001-07-17
申请人： Hiroshi Miyaguchi , Takao Kojima
发明人： Hiroshi Miyaguchi , Takao Kojima
IPC分类号： H04N1/17 , H04N5/907
CPC分类号： H04N1/32443 , G06K15/00 , H04N1/32358 , H04N2201/3287 , H04N2201/3292
摘要： The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selected by selector 29 and written to output line memory 24 at a speed n times faster than the speed of the input image data; the output image data are read in units of one scan line from output line memory 24 at a prescribed speed.
摘要翻译：本发明的目的是提供即使在低速执行相对于外部的输入/输出的情况下也能高速运转的图像处理装置，并且可以通过输入行存储器23和输出完全利用可处理性行存储器24，其可以存储一条扫描线的图像数据，并分别布置在输入单元和输出单元中; 输入图像数据以输入图像数据的速度写入输入行存储器23; 已经写入输入行存储器的图像数据以比输入图像数据快n倍的速度读取，并被发送到处理单元25或存储器单元26; 处理单元25和存储单元26以比输入图像数据的速度快n倍的速度接收一条扫描线的图像数据，执行规定的处理，然后以比速度快n倍的速度输出处理结果的输入图像数据; 从处理单元25或存储单元26输出的图像数据由选择器29选择并以比输入图像数据的速度快n倍的速度写入输出行存储器24; 输出图像数据以规定速度从输出行存储器24以一条扫描线为单位读取。

14. 发明授权

US06763450B1 Processor 有权
标题翻译：处理器
公开(公告)号：US06763450B1
公开(公告)日：2004-07-13
申请号：US09680609
申请日：2000-10-06
申请人： Hiroshi Miyaguchi , Tsuyoshi Akiyama , Hidetoshi Onuma
发明人： Hiroshi Miyaguchi , Tsuyoshi Akiyama , Hidetoshi Onuma
IPC分类号： G06F938
CPC分类号： G06F9/3885 , G06F9/325
摘要： The objective of the invention is to improve the processing efficiency of a system that repeatedly executes one instruction over multiple clock cycles. The SVP core 12 of this SVP (Scan-line Video Processor) 10 is made up of a three layer construction of the data input register (DIR) 16, the SIMD type digital signal processing unit 18, and the data output register (DOR) 20. The SIMD type digital signal processing unit 18 comprises a parallel arranged (connected) number of processing elements (PE0 to PEN−1) (for example, 864 units) equal to the number of pixels N on one horizontal scan line. The instruction generator (IG) 14, because the SVP core 12 operates as an SIMD parallel processor, internally houses a RAM or ROM program memory that holds the desired program. The program stored in program memory contains not only the instructions (SIMD instruction) for the processing elements (PE0 to PEN−1) of the processing unit 18, but also such instructions (IG instruction) as jump, subroutine call, hardware interrupt, and the like. In this SVP 10, when an IG instruction is read from the program memory while the repetitive processing of an SIMD instruction is being conducted in the SVP core 12, the pertinent IG instruction is executed in parallel with the repetitive processing of the pertinent SIMD instruction.
摘要翻译：本发明的目的是提高在多个时钟周期内重复执行一个指令的系统的处理效率。该SVP（扫描线视频处理器）10的SVP核心12由数据输入寄存器（DIR）16，SIMD型数字信号处理单元18和数据输出寄存器（DOR）的三层结构组成， SIMD型数字信号处理单元18包括与一个水平扫描线上的像素数N相等的并行布置（连接）数量的处理元件（PE0至PEN-1）（例如，864单位）。指令发生器（IG）14，由于SVP核心12作为SIMD并行处理器操作，所以内部容纳保存所需程序的RAM或ROM程序存储器。存储在程序存储器中的程序不仅包含处理单元18的处理元件（PE0至PEN-1）的指令（SIMD指令），还包含跳转，子程序调用，硬件中断和类似。在该SVP10中，当在SVP核心12中进行SIMD指令的重复处理时从程序存储器读取IG指令时，与相关的SIMD指令的重复处理并行地执行相关的IG指令。

15. 发明授权

US5499375A Feedback register configuration for a synchronous vector processor employing delayed and non-delayed algorithms 失效
标题翻译：采用延迟和非延迟算法的同步向量处理器的反馈寄存器配置
公开(公告)号：US5499375A
公开(公告)日：1996-03-12
申请号：US105198
申请日：1993-08-09
申请人： Hiroshi Miyaguchi
发明人： Hiroshi Miyaguchi
IPC分类号： G06F15/80 , G06T1/20 , G09G5/02 , G09G5/395 , G06F15/00 , G06F15/76 , G06F15/64
CPC分类号： G06F15/8015 , G06T1/20 , G09G5/02 , G09G5/395
摘要： A Serial Video Processor (SVP) is provided for processing data through a plurality of parallel processing elements (228). Data is first stored in a data input register (DIR) (222) and then processed through the PE (228). The data is then output into a Data Output Register (DOR) (230). During one pass of data through the PE (228), a variable is calculated and stored in an auxiliary register (242). This auxiliary value is typically selected from one of the processing elements representing a value over the entire or part of the input vector of data. A multiplexer (248) selects this value from the output value stored in the register (242) and then inputs it to a second multiplexer (240). The second multiplexer (240) is operable to select either a predefined variable from either another auxiliary register (238) or from an instruction generator ROM (236), or select the precalculated variable stored in the register (242). When the variable in the register (242) is selected, it is globally spread over the entire PE ( 228) for utilization in a subsequent calculation. In the subsequent calculation, the data utilized to generate the variable was delayed to generate the variable and then utilize the variable in a present calculation.
摘要翻译：串行视频处理器（SVP）被提供用于通过多个并行处理元件（228）处理数据。数据首先存储在数据输入寄存器（DIR）（222）中，然后通过PE处理（228）。然后将数据输出到数据输出寄存器（DOR）（230）。在通过PE（228）的数据通过期间，计算变量并将其存储在辅助寄存器（242）中。该辅助值通常从表示数据的输入向量的整个或部分的值的处理元素之一中选择。复用器（248）从存储在寄存器（242）中的输出值中选择该值，然后将其输入到第二多路复用器（240）。第二多路复用器（240）可操作以从另一辅助寄存器（238）或指令生成器ROM（236）中选择预定变量，或选择存储在寄存器（242）中的预先计算的变量。当选择寄存器（242）中的变量时，它将全局扩展到整个PE（228）上，以供后续计算使用。在随后的计算中，用于生成变量的数据被延迟以生成变量，然后在当前计算中利用该变量。

16. 发明授权

US5293637A Distribution of global variables in synchronous vector processor 失效
标题翻译：全局变量在同步向量处理器中的分布
公开(公告)号：US5293637A
公开(公告)日：1994-03-08
申请号：US76277
申请日：1993-06-10
申请人： Jim Childers , Hiroshi Miyaguchi
发明人： Jim Childers , Hiroshi Miyaguchi
IPC分类号： F02B75/02 , G06F15/80 , G06T1/20 , G06F15/64
CPC分类号： G06F15/8007 , G06T1/20 , F02B2075/027
摘要： A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and the SVP is capable of real-time digital processing of video signals. In video applications a data input control circuit including a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit is provided. In order to distribute variables to each processor element simultaneously the data input control circuit is provided with a set of auxiliary registers and an addressing structure to modulate one of the processor elements' working registers. In this manner variables are provided to the SVP device in lieu of a designated control instruction bit.
摘要翻译：具有以线性阵列组织的多个一位处理器元件的同步矢量处理器SVP装置。处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且SVP能够对视频信号进行实时数字处理。在视频应用中，提供了包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路的数据输入控制电路。为了同时将变量分配给每个处理器元件，数据输入控制电路设置有一组辅助寄存器和寻址结构，以调制处理器元件的工作寄存器之一。以这种方式，将变量提供给SVP设备来代替指定的控制指令位。

17. 发明授权

US5163120A Second nearest-neighbor communication network for synchronous vector processor, systems and methods 失效
标题翻译：用于同步向量处理器的第二最近邻通信网络，系统和方法
公开(公告)号：US5163120A
公开(公告)日：1992-11-10
申请号：US421499
申请日：1989-10-13
申请人： Jim Childers , Peter Reinecke , Hiroshi Miyaguchi
发明人： Jim Childers , Peter Reinecke , Hiroshi Miyaguchi
IPC分类号： F02B75/02 , G06F15/80
CPC分类号： G06F15/8015 , F02B2075/027
摘要： A synchronous vector processor SVP device having a plurality of one-bit processor elements organized in a linear array. The processor elements are all controlled in common by a sequencer, a state machine or a control circuit (controller) to enable operation as a parallel processing device. Each processor element includes a set of input registers, two sets of register files, a set of working registers, an arithmetic logic unit including a one-bit full adder/subtractor, and a set of output registers. In video applications each processor element operates on one pixel of a horizontal scan line and is capable of real-time digital processing of video signals. The SVP includes interconnecting circuitry enabling the individual processor elements to retrieve data from and transmit data to their first and second nearest neighbors on either side. At the chip level external connections are provided to enable cascading of several SVP devices.
摘要翻译：具有以线性阵列组织的多个一位处理器元件的同步矢量处理器SVP装置。处理器元件都由序列发生器，状态机或控制电路（控制器）共同控制，以使得能够作为并行处理装置进行操作。每个处理器元件包括一组输入寄存器，两组寄存器文件，一组工作寄存器，包括一位全加器/减法器的算术逻辑单元和一组输出寄存器。在视频应用中，每个处理器元件在水平扫描线的一个像素上操作，并且能够对视频信号进行实时数字处理。 SVP包括互连电路，使得各个处理器元件能够从两侧检索数据并向其第一和第二最近邻居发送数据。在芯片级别，提供外部连接以实现若干SVP设备的级联。

18. 发明授权

US5091786A Multi-screen feature for improved definition television digital processing units, systems, and methods 失效
标题翻译：多屏幕功能，用于改进的定义电视数字处理单元，系统和方法
公开(公告)号：US5091786A
公开(公告)日：1992-02-25
申请号：US486666
申请日：1990-03-01
申请人： Hiroshi Miyaguchi
发明人： Hiroshi Miyaguchi
IPC分类号： H04N5/14 , H04N5/208 , H04N5/44 , H04N5/45 , H04N9/64 , H04N9/78
CPC分类号： H04N5/4448 , H04N5/144 , H04N5/208 , H04N5/44 , H04N5/45 , H04N7/012 , H04N9/646 , H04N9/78
摘要： A television receiving system includes a digital unit, which has at least one single-instruction multiple-data processor, especially suited for television processing. The processor receives data samples of each horizontal line word-serially, but processes the line in parallel. The processor has input, computational, and output layers that operate concurrently. Internal register files emulate line memory to eliminate the need for external line memories. The processor may be programmed with various improved definition television tasks, downloaded to it from a host development system. Field memories and multiplexers control the data flow so that a sub-picture and a full size picture may be displayed at one time.
摘要翻译：电视接收系统包括具有至少一个特别适用于电视处理的单指令多数据处理器的数字单元。处理器串行地接收每个水平行字的数据样本，但并行处理该行。处理器具有并发操作的输入，计算和输出层。内部寄存器文件模拟行存储器，以消除对外部线路存储器的需要。处理器可以用从主机开发系统下载到其中的各种改进的定义电视任务进行编程。场存储器和多路复用器控制数据流，使得可以一次显示子画面和全尺寸画面。

19. 发明申请

US20090324039A1 SYSTEM AND METHOD FOR CONVERTING SCAN DATA 有权
标题翻译：用于转换扫描数据的系统和方法
公开(公告)号：US20090324039A1
公开(公告)日：2009-12-31
申请号：US12164680
申请日：2008-06-30
申请人： Hiroshi Miyaguchi
发明人： Hiroshi Miyaguchi
IPC分类号： G06K9/00
CPC分类号： G06T3/00
摘要： An ultrasound device generates polar-coordinate image data divided up into an (N×M) array of polar-coordinate image data blocks; a first external memory configured to store the (N×M) array of data blocks; a second external memory configured to store x-y coordinate image data corresponding to the polar-coordinate image data; a video processing chip comprising an internal memory configured to store an (N×R) array of the polar-coordinate image data blocks; and a controller configured to perform a data conversion operation on the (N×R) array of data blocks to generate x-y coordinate image data, and to store the x-y coordinate image data to the second external memory. N, M, and R are integers greater than 1; R is less than M; and an internal access time for the internal memory element is shorter than an external access time for the first external memory element.
摘要翻译：超声波装置生成被分割成极坐标图像数据块的（N×M）阵列的极坐标图像数据; 第一外部存储器，被配置为存储数据块的（N×M）阵列; 第二外部存储器，被配置为存储与所述极坐标图像数据相对应的x-y坐标图像数据; 视频处理芯片，包括被配置为存储所述极坐标图像数据块的（NxR）阵列的内部存储器; 以及控制器，其被配置为对数据块的（NxR）阵列执行数据转换操作以生成x-y坐标图像数据，并将x-y坐标图像数据存储到第二外部存储器。 N，M和R是大于1的整数; R小于M; 并且内部存储器元件的内部访问时间比第一外部存储器元件的外部访问时间短。

20. 发明授权

US6128733A Program loading method and apparatus 有权
标题翻译：程序加载方法和装置
公开(公告)号：US6128733A
公开(公告)日：2000-10-03
申请号：US165574
申请日：1998-10-02
申请人： Hiroshi Miyaguchi , Naoya Tokunaga
发明人： Hiroshi Miyaguchi , Naoya Tokunaga
IPC分类号： G06F9/06 , G06F9/445 , G06F15/177
CPC分类号： G06F9/445
摘要： A method for loading of program data with high speed and efficiency along with eliminating the need for software modification even if changes occur in the storage addresses and data length of the program data stored in the program memory. In order to load program data in a rewritable manner into a number of functional circuits FC0, FC1, . . . , FCn operating in accordance with the supplied program data, a program memory, for example, a ROM 10, a program loader 12, and program designating apparatus, for example, a microprocessor 14, are provided in the system. In the ROM 10, multiple address pointers are stored in specified storage areas, and corresponding sets of program data are stored in the storage locations indicated by the address pointers in such a manner that a first set of program data is stored in the specified storage area which utilizes the address corresponding to the first address pointer as the start storage address, and a second set of program data is stored in the specified storage area which utilizes the address corresponding to the second address pointer as the start storage address.
摘要翻译：一种用于以高速度和高效率加载程序数据的方法，即使存储在程序存储器中的程序数据的存储地址和数据长度发生变化也不需要软件修改。为了将程序数据以可重写的方式加载到多个功能电路FC0，FC1，...中。。。，根据提供的程序数据操作的FCn，在系统中提供程序存储器，例如ROM 10，程序加载器12和程序指定装置，例如微处理器14。在ROM10中，多个地址指针被存储在指定的存储区域中，并且相应的程序数据组被存储在由地址指针指示的存储位置中，使得第一组程序数据被存储在指定的存储区域其利用与第一地址指针相对应的地址作为开始存储地址，并且将第二组程序数据存储在利用与第二地址指针相对应的地址作为起始存储地址的指定存储区域中。

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