专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明申请

US20120239904A1 SEAMLESS INTERFACE FOR MULTI-THREADED CORE ACCELERATORS 有权
标题翻译：多线程加速器的无缝接口
公开(公告)号：US20120239904A1
公开(公告)日：2012-09-20
申请号：US13048214
申请日：2011-03-15
申请人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
发明人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
IPC分类号： G06F9/30 , G06F12/10
CPC分类号： G06F9/3877 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F12/1027
摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.
摘要翻译：公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换。只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。这有助于启动指定的操作而不会出现内存转换错误在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

12. 发明申请

US20110138101A1 MAINTAINING DATA COHERENCE BY USING DATA DOMAINS 失效
标题翻译：通过使用数据域维护数据的一致性
公开(公告)号：US20110138101A1
公开(公告)日：2011-06-09
申请号：US12633428
申请日：2009-12-08
申请人： Kattamuri Ekanadham , Il Park , Pratap Pattnaik
发明人： Kattamuri Ekanadham , Il Park , Pratap Pattnaik
IPC分类号： G06F12/06
CPC分类号： G06F9/30007 , G06F12/0817 , G06F12/1027
摘要： A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.
摘要翻译：公开了用于维持数据一致性的方法，系统和计算机程序产品，用于多节点处理系统，其中每个节点包括一个或多个组件。在一个实施例中，该方法包括建立数据域，将一组组件分配给数据域，将相干消息从处理系统的第一组件发送到处理系统的第二组件，以及确定该第二组件被分配给数据域。在该实施例中，如果该第二组件被分配给数据域，则将相干消息传送到分配给数据域的所有组件，以维持这些组件之间的数据一致性。在一个实施例中，如果将该第二组件分配给数据域，则将第一组件分配给数据域。

13. 发明申请

US20090216956A1 SYSTEM, METHOD AND COMPUTER PROGRAM PRODUCT FOR ENHANCING TIMELINESS OF CACHE PREFETCHING 有权
标题翻译：系统，方法和计算机程序产品，用于增强缓存时间的推广
公开(公告)号：US20090216956A1
公开(公告)日：2009-08-27
申请号：US12036476
申请日：2008-02-25
申请人： Kattamuri Ekanadham , Jennifer A. Navarro , Il Park , Chung-Lung Kevin Shum
发明人： Kattamuri Ekanadham , Jennifer A. Navarro , Il Park , Chung-Lung Kevin Shum
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6026
摘要： A system, method, and computer program product for enhancing timeliness of cache memory prefetching in a processing system are provided. The system includes a stride pattern detector to detect a stride pattern for a stride size in an amount of bytes as a difference between successive cache accesses. The system also includes a confidence counter. The system further includes eager prefetching control logic for performing a method when the stride size is less than a cache line size. The method includes adjusting the confidence counter in response to the stride pattern detector detecting the stride pattern, comparing the confidence counter to a confidence threshold, and requesting a cache prefetch in response to the confidence counter reaching the confidence threshold. The system may also include selection logic to select between the eager prefetching control logic and standard stride prefetching control logic.
摘要翻译：提供了一种用于增强处理系统中的高速缓存存储器预取的及时性的系统，方法和计算机程序产品。系统包括步幅图案检测器，用于检测作为连续高速缓存访问之间的差异的字节量的步幅大小的步幅图案。系统还包括置信柜台。该系统还包括用于当步幅大小小于高速缓存行大小时执行方法的迫切预取控制逻辑。该方法包括响应于步幅模式检测器检测步幅模式来调整置信计数器，将置信计数器与置信阈值进行比较，以及响应于达到置信阈值的置信度计数器请求高速缓存预取。系统还可以包括选择逻辑以在急切预取控制逻辑和标准步幅预取控制逻辑之间进行选择。

14. 发明申请

US20050091643A1 Control flow based compression of execution traces 有权
标题翻译：基于控制流的压缩执行跟踪
公开(公告)号：US20050091643A1
公开(公告)日：2005-04-28
申请号：US10695139
申请日：2003-10-28
申请人： Kattamuri Ekanadham , Pratap Pattnaik , Simone Sbaraglia , Luiz DeRose
发明人： Kattamuri Ekanadham , Pratap Pattnaik , Simone Sbaraglia , Luiz DeRose
IPC分类号： G06F3/00 , G06F9/44 , G06F11/34
CPC分类号： G06F11/3471 , G06F11/3476 , G06F2201/86
摘要： A method and apparatus for creating a compressed trace for a program, wherein events are compressed separately to provide improved compression and tracing. A sequence of events for a program is selected, and a sequence of values is then determined for each of the selected events occurring during an execution of the program. Each sequence of values is then compressed to generate a compressed sequence of values for each event. These values are then ordered in accordance with information stored in selected events (such as for example, branch events), where the ordered values correspond to the trace.
摘要翻译：一种用于为程序创建压缩轨迹的方法和装置，其中分别压缩事件以提供改进的压缩和跟踪。选择程序的事件序列，然后针对在执行程序期间发生的每个所选择的事件确定一系列值。然后将每个值序列压缩以产生每个事件的压缩的值序列。这些值然后根据存储在所选事件（例如分支事件）中的信息进行排序，其中有序值对应于跟踪。

15. 发明授权

US06321373B1 Method for resource control in parallel environments using program organization and run-time support 失效
标题翻译：使用程序组织和运行时支持的并行环境中的资源控制方法
公开(公告)号：US06321373B1
公开(公告)日：2001-11-20
申请号：US09431107
申请日：1999-10-30
申请人： Kattamuri Ekanadham , Jose Eduardo Moreira , Vijay Krishnarao Naik
发明人： Kattamuri Ekanadham , Jose Eduardo Moreira , Vijay Krishnarao Naik
IPC分类号： G06F944
CPC分类号： G06F9/5077
摘要： A system and method for dynamic scheduling and allocation of resources to parallel applications during the course of their execution. By establishing well-defined interactions between an executing job and the parallel system, the system and method support dynamic reconfiguration of processor partitions, dynamic distribution and redistribution of data, communication among cooperating applications, and various other monitoring actions. The interactions occur only at specific points in the execution of the program where the aforementioned operations can be performed efficiently.
摘要翻译：一种在并行应用程序执行过程中动态调度和分配资源的系统和方法。通过建立执行作业与并行系统之间的明确定义的交互，系统和方法支持处理器分区的动态重新配置，数据的动态分配和重新分配，协作应用之间的通信以及各种其他监控动作。相互作用仅在执行上述操作有效执行的程序的特定点处发生。

16. 发明申请

US20110238962A1 Register Checkpointing for Speculative Modes of Execution in Out-of-Order Processors 审中-公开
标题翻译：在无序处理器中注册执行的投机模式的注册点
公开(公告)号：US20110238962A1
公开(公告)日：2011-09-29
申请号：US12729282
申请日：2010-03-23
申请人： Harold W. Cain, III , Kattamuri Ekanadham , IL Park
发明人： Harold W. Cain, III , Kattamuri Ekanadham , IL Park
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/3842 , G06F9/3863
摘要： A mechanism is provided for generating a checkpoint for a speculatively executed portion of code. The mechanisms identify, during a speculative execution of a portion of code, a register renaming operation occurring to an entry in a register renaming table of the processor. In response to the register renaming operation occurring to the register renaming table, a determination is made as to whether an update to an entry in a hardware-implemented recovery renaming table is to be performed. If so, the entry in the hardware-implemented recovery renaming table is updated. The entry in the recovery renaming table is part of the checkpoint for the speculative execution of the portion of code.
摘要翻译：提供了一种用于生成用于推测性地执行的代码部分的检查点的机制。机构在推测执行代码的一部分期间识别发生在处理器的寄存器重命名表中的条目的寄存器重命名操作。响应于对寄存器重命名表发生的寄存器重命名操作，确定是否执行对硬件实现的恢复重命名表中的条目的更新。如果是这样，则更新硬件实现的恢复重命名表中的条目。恢复重命名表中的条目是对部分代码的推测执行的检查点的一部分。

17. 发明申请

US20110138125A1 EVENT TRACKING HARDWARE 有权
标题翻译：事件跟踪硬件
公开(公告)号：US20110138125A1
公开(公告)日：2011-06-09
申请号：US12630946
申请日：2009-12-04
申请人： Kattamuri Ekanadham , Il Park
发明人： Kattamuri Ekanadham , Il Park
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F11/348 , G06F12/0875 , G06F2201/88
摘要： An event tracking hardware engine having N (≧2) caches is invoked when an event of interest occurs, using a corresponding key. The engine stores, for each of the different kinds of events, a corresponding cumulative number of occurrences, by carrying out additional steps. In some instances, the additional steps include searching in the N caches for an entry for the key; if an entry for the key is found, and no overflow of the corresponding cumulative number of occurrences for the entry for the key would occur by incrementing the corresponding cumulative number of occurrences, incrementing; if the entry for the key is found, and overflow would occur, promoting the entry to a next highest cache; and if the entry for the key is not found, entering the entry for the key in a zeroth one of the caches with the corresponding cumulative number of occurrences being initialized. In other instances, the additional steps include searching in a zeroth one of the caches for an entry for the key; if an entry for the key is found in the zeroth one of the caches, and no overflow of the corresponding cumulative number of occurrences for the entry for the key would occur by incrementing the corresponding cumulative number of occurrences, incrementing; if the entry for the key is found in the zeroth one of the caches, and overflow would occur, promoting the entry from the zeroth one of the caches in which the entry exists to a next highest cache; and if the entry for the key is not found, entering the entry for the key in the zeroth one of the caches with the corresponding cumulative number of occurrences being initialized. The engine includes a plurality of caches and a corresponding plurality of control circuits.
摘要翻译：使用对应的密钥，当感兴趣的事件发生时，调用具有N（≥2）个高速缓存的事件跟踪硬件引擎。通过执行附加步骤，发动机为每种不同类型的事件存储相应的累积出现次数。在某些情况下，附加步骤包括在N个高速缓存中搜索密钥的条目; 如果找到密钥的条目，并且通过增加相应的累积出现次数而不会发生用于密钥的条目的相应累积出现次数的溢出，则递增; 如果找到密钥的条目，并发生溢出，则将条目提升到下一个最高的缓存; 并且如果没有找到密钥的条目，则在具有对应的累积出现次数被初始化的高速缓存中的第零个密码中输入密钥的条目。在其他情况下，附加步骤包括在第一个高速缓存中搜索用于密钥的条目; 如果在第一个高速缓存中找到密钥的条目，并且通过增加相应的累积出现次数将增加密钥的入口的相应累积出现次数的溢出，如果在第一个高速缓存中找到密钥的条目，并且将发生溢出，则将条目存在的高速缓存中的第一个提升到下一个最高缓存; 并且如果没有找到密钥的条目，则在具有对应的累积出现次数被初始化的第一个高速缓存中输入密钥的条目。发动机包括多个高速缓存和相应的多个控制电路。

18. 发明申请

US20090150874A1 BINARY PROGRAMMABLE METHOD FOR APPLICATION PERFORMANCE DATA COLLECTION 有权
标题翻译：应用性能数据收集的二进制可编程方法
公开(公告)号：US20090150874A1
公开(公告)日：2009-06-11
申请号：US11952922
申请日：2007-12-07
申请人： I-Hsin Chung , Kattamuri Ekanadham , David Joseph Klepacki , Simone Sbaraglia , Robert Edward Walkup , Hui-Fang Wen , Hao Yu
发明人： I-Hsin Chung , Kattamuri Ekanadham , David Joseph Klepacki , Simone Sbaraglia , Robert Edward Walkup , Hui-Fang Wen , Hao Yu
IPC分类号： G06F9/45 , G06F9/44
CPC分类号： G06F11/3466 , G06F8/4441 , G06F2201/865
摘要： A method for application performance data collection includes steps or acts of: customizing a performance tool for collecting application performance data of an application; modifying the application by inserting the performance tool while the application does not need to be rebuilt from the source; executing the application; and collecting the application execution performance data such that only interesting data is collected. Customizing the performance tool proceeds by implementing at least one configurable tracing function that can be programmed by the user; compiling the function(s) into an object file; and inserting the object file into the performance tool using binary instrumentation.
摘要翻译：应用性能数据收集的方法包括以下步骤或动作：定制用于收集应用的应用性能数据的性能工具; 通过插入性能工具来修改应用程序，同时不需要从源重建应用程序; 执行应用程序; 并收集应用执行性能数据，使得只收集有趣的数据。通过实现可由用户编程的至少一个可配置跟踪功能来自定义性能工具; 将函数编译成对象文件; 并使用二进制检测将目标文件插入性能工具。

19. 发明授权

US5802288A Integrated communications for pipelined computers 失效
标题翻译：流水线计算机集成通信
公开(公告)号：US5802288A
公开(公告)日：1998-09-01
申请号：US589076
申请日：1996-01-23
申请人： Kattamuri Ekanadham , Ronald Mraz
发明人： Kattamuri Ekanadham , Ronald Mraz
IPC分类号： G06F13/38 , G06F15/173
CPC分类号： G06F13/387
摘要： This document describes a feature that can be added to existing pipelined architectures (such as RISC) to enhance packet based or message passing communications. The feature integrates the communication interface directly into the pipeline of the processor, offering the potential to greatly reduce latency and overhead for fine grain communications. Additionally, a second interface is provided to maintain high bandwidth for large blocks of data.
摘要翻译：本文档描述了可以添加到现有流水线架构（例如RISC）中以增强基于分组或消息传递通信的特征。该功能将通信接口直接集成到处理器的流水线中，提供了大幅度减少细粒度通信的延迟和开销的潜力。此外，提供第二接口以维持大数据块的高带宽。

20. 发明授权

US08683175B2 Seamless interface for multi-threaded core accelerators 有权
标题翻译：多线程核心加速器的无缝界面
公开(公告)号：US08683175B2
公开(公告)日：2014-03-25
申请号：US13048214
申请日：2011-03-15
申请人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
发明人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
IPC分类号： G06F9/30 , G06F12/10
CPC分类号： G06F9/3877 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F12/1027
摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.
摘要翻译：公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换。只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。这有助于启动指定的操作，而不会出现内存转换错误。在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式