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11. 发明授权

US5376215A Apparatus for production of extremely thin SOI film substrate 失效
标题翻译：用于生产极薄SOI薄膜基片的设备
公开(公告)号：US5376215A
公开(公告)日：1994-12-27
申请号：US151209
申请日：1993-11-12
申请人： Yutaka Ohta , Masatake Nakano , Masatake Katayama , Takao Abe
发明人： Yutaka Ohta , Masatake Nakano , Masatake Katayama , Takao Abe
IPC分类号： H01L21/302 , G01B11/06 , H01L21/3065 , H01L21/66 , H01L21/762 , H01L27/12 , B44C1/22 , C03C15/00 , H01L21/306
CPC分类号： H01L21/76251 , G01B11/0683 , H01L21/3065 , H01L22/12 , H01L22/20
摘要： A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
摘要翻译：通过由紫外光激发的化学气相腐蚀的反应使接合的SOI（绝缘体上硅）层均匀化的方法和装置，其有效和方便地实现膜厚度的测量，从而实现对在每次测量时，不需要从用于化学气相腐蚀的反应容器中除去衬底的薄膜层的厚度分散，或者需要安装用于改变反应容器内部或外部的测量位置的机构被披露。通过保持观察由于膜层的厚度分布引起的干涉条纹来进行膜厚度的测量。

12. 发明授权

US5240883A Method of fabricating SOI substrate with uniform thin silicon film 失效
标题翻译：用均匀的薄膜制造SOI衬底的方法
公开(公告)号：US5240883A
公开(公告)日：1993-08-31
申请号：US841166
申请日：1992-02-25
申请人： Takao Abe , Masatake Katayama , Akio Kanai , Konomu Ohki , Masatake Nakano
发明人： Takao Abe , Masatake Katayama , Akio Kanai , Konomu Ohki , Masatake Nakano
IPC分类号： H01L21/02 , H01L21/20 , H01L21/304 , H01L21/3063 , H01L21/762 , H01L27/12
CPC分类号： H01L21/2007 , H01L21/3063 , H01L21/76251 , Y10S148/127 , Y10S148/135 , Y10S438/924
摘要： A thin Silicon film On Insulator (SOI) material fabricating method which is capable of providing a very high thickness uniformity of the silicon film, a process simplification and a considerable reduction of processing cost is disclosed, in which a silicon oxide film is formed on one or both of a p-type silicon bond wafer and a silicon base wafer, then the two wafers are bonded together through the silicon oxide film, subsequently a fixed positive charge is induced in the silicon oxide film to form a n-type inversion layer in the p-type silicon bond wafer adjacent to an interface between the p-type silicon bond wafer and the silicon oxide film layer, and thereafter a chemical etching is effected while applying a positive voltage to the p-type silicon bond wafer so that an etch-stop is made at an interface between a depletion layer including the n-type inversion layer and the p-type layer.

13. 发明授权

US5124274A Method for production of dielectric-separation substrate 失效
标题翻译：电介质分离基板的制造方法
公开(公告)号：US5124274A
公开(公告)日：1992-06-23
申请号：US791518
申请日：1991-11-14
申请人： Konomu Ohki , Yutaka Ohta , Masatake Katayama
发明人： Konomu Ohki , Yutaka Ohta , Masatake Katayama
IPC分类号： H01L21/3213 , H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/32136 , H01L21/76264 , H01L21/76297 , H01L21/763 , H01L21/76275 , H01L21/76286
摘要： After the separating grooves has been formed, the polycrystalline silicon deposited as bonded to the single crystal substrate as a supporting base, and the polycrystalline silicon layer ground and polished until the oxide film in the area other than the separating grooves is exposed, the present invention etches the polycrystalline silicon layer on the separating grooves with mixed acid composed of hydrofluoric acid and nitric acid until its thickness equals that of the separating oxide film and subsequently removes the oxide film in the area other than the separating grooves with hydrofluoric acid, As a result, the otherwise inevitable occurrence of projections of polycrystalline silicon can be precluded. When the dielectric-separation substrate obtained by the present invention is used in manufacturing a semiconductor device, therefore, the occurrence of particles due to the chipping of the projections of polycrystalline silicon and the breakage of distributed wires in the produced device can be prevented.

14. 发明授权

US06254933B1 Method of chemical vapor deposition 有权
标题翻译：化学气相沉积方法
公开(公告)号：US06254933B1
公开(公告)日：2001-07-03
申请号：US09395848
申请日：1999-09-14
申请人： Hitoshi Habuka , Masanori Mayuzumi , Naoto Tate , Masatake Katayama
发明人： Hitoshi Habuka , Masanori Mayuzumi , Naoto Tate , Masatake Katayama
IPC分类号： C23C1600
CPC分类号： C30B25/08 , C23C16/455 , C30B25/14
摘要： A method of performing chemical vapor deposition which produces semiconductor crystalline thin films having small transition widths. The method involves the use of a cold-wall type reaction chamber that is equipped with a gas inlet at one end and a gas outlet at the other end and a semiconductor substrate support which supports a semiconductor substrate so that a main surface thereof is horizontal. A reactant gas is caused to flow horizontally through the reaction chamber to effect the growing of a crystalline thin film on the main surface of the semiconductor substrate. The semiconductor substrate is arranged within the reactor chamber within a distance W which is measured from a leading edge of the semiconductor substrate at a most upstream position along a direction toward the gas outlet where W indicates an internal width of the reaction chamber. The semiconductor substrate is also in a location having a W/G ratio of 15 or greater, where G represents a distance between the main surface of the semiconductor substrate and a ceiling of the reaction chamber.
摘要翻译：一种进行化学气相沉积的方法，其产生具有小转变宽度的半导体晶体薄膜。该方法包括使用在一端配备气体入口和另一端的气体出口的冷壁式反应室，以及支撑半导体衬底以使其主表面为水平的半导体衬底支撑件。使反应气体水平地流过反应室，以在半导体衬底的主表面上生长晶体薄膜。将半导体衬底布置在反应器室内的距离W内，该距离W是沿着朝向气体出口的方向的最上游位置从半导体衬底的前缘测量的，其中W表示反应室的内部宽度。半导体衬底也处于W / G比为15或更大的位置，其中G表示半导体衬底的主表面和反应室的顶部之间的距离。

15. 发明授权

US5718762A Method for vapor-phase growth 失效
标题翻译：气相生长方法
公开(公告)号：US5718762A
公开(公告)日：1998-02-17
申请号：US607566
申请日：1996-02-27
申请人： Hitoshi Habuka , Naoto Tate , Masanori Mayuzumi , Hitoshi Tsunoda , Masatake Katayama
发明人： Hitoshi Habuka , Naoto Tate , Masanori Mayuzumi , Hitoshi Tsunoda , Masatake Katayama
IPC分类号： C30B29/06 , C23C16/02 , C30B25/02 , C30B33/12 , H01L21/205 , H01L21/302 , H01L21/3065 , C30B25/20
CPC分类号： C30B29/06 , C30B25/02
摘要： A method for vapor-phase growth which allows an epiwafer of a smooth surface free from microroughness to be produced is provided. This method comprises a step of heating up a silicon single crystal substrate in an ambience of an inert gas started at a temperature of less than 800.degree. C. and a step of removing a native oxide film formed on the surface of the silicon single crystal substrate by etching with hydrogen gas in an ambience of hydrogen gas at a temperature of not less than 950.degree. C. and not more than 1190.degree. C. prior to the vapor-phase growth.
摘要翻译：提供了一种气相生长方法，其允许产生没有微粗糙度的光滑表面的外延膜。该方法包括在低于800℃的温度下开始的惰性气体的氛围中加热硅单晶衬底的步骤，以及去除在硅单晶衬底的表面上形成的自然氧化膜的步骤在气相生长前，在不低于950℃，不高于1190℃的氢气气氛中用氢气蚀刻。

16. 发明授权

US5223080A Method for controlling thickness of single crystal thin-film layer in SOI substrate 失效
标题翻译：控制SOI衬底中单晶薄膜厚度的方法
公开(公告)号：US5223080A
公开(公告)日：1993-06-29
申请号：US799182
申请日：1991-11-27
申请人： Yutaka Ohta , Masatake Katayama , Takao Abe , Yasuaki Nakazato
发明人： Yutaka Ohta , Masatake Katayama , Takao Abe , Yasuaki Nakazato
IPC分类号： H01L21/66 , C30B33/00 , G01B11/06 , H01L21/20 , H01L21/302 , H01L21/3065 , H01L21/762 , H01L21/84
CPC分类号： C30B29/06 , C30B33/00 , G01B11/0683 , H01L21/3065 , H01L21/76251 , H01L22/12 , H01L22/20
摘要： A method for controlling the thickness of a single crystal thin-film silicon layer bonded on a dielectric substrate in a SOI substrate thereby effecting conversion of said single crystal silicon layer to a thin film is disclosed. To be more precise, said method comprises selectively and hypothetically dividing the entire surface of said single crystal silicon layer destined to undergo a chemical vapor-phase corrosion reaction for the sake of said conversion into necessary minute sections and, at the sametime, taking preparatory measurement of the thickness of said single crystal silicon layer in each of said minute sections, and effecting on each of said minute sections said conversion to a thin film by a chemical vapor-phase corrosion reaction adjusted in accordance with the measured thickness of layer. The conversion to a thin film is attained with the dispersion of thickness of the single crystal silicon layer controlled with high accuracy.

17. 发明授权

US6008128A Method for smoothing surface of silicon single crystal substrate 失效
标题翻译：硅单晶衬底表面平滑化方法
公开(公告)号：US6008128A
公开(公告)日：1999-12-28
申请号：US105155
申请日：1998-06-26
申请人： Hitoshi Habuka , Toru Otsuka , Masatake Katayama
发明人： Hitoshi Habuka , Toru Otsuka , Masatake Katayama
IPC分类号： H01L21/302 , H01L21/205 , H01L21/304 , H01L21/306
CPC分类号： H01L21/02046
摘要： A method for microscopically smoothing a surface of a wafer made of silicon single crystal having a low resistivity. In the method, a native oxide film grown on a surface of a wafer having polished by an ordinary mirror polishing process is removed at a temperature of less than 100.degree. C. with use of a mixture gas of HF and H.sub.2, and then an organic substance deposited thereon is removed at a temperature of less than 800.degree. C. with use of a mixture gas of HCl and H.sub.2. Re-growth of an oxide film is suppressed in a consistent H.sub.2 atmosphere, during which the wafer is substantially not varied in its surface roughness. Then the wafer is thermally treated in an H.sub.2 gas atmosphere at a temperature of not less than 800.degree. C. and less than 1000.degree. C. A process of etching the silicon single crystal substrate and a process of depositing silicon atoms caused by decomposition of a silane compound generated are competitively carried out to thereby soften the microscopic rough surface of the wafer and to improve a smoothness over the smoothness of the mirror-polished surface. Since all process temperatures are set to be less than 1000.degree. C., vaporization of impurities in the wafer can be suppressed and its low resistivity can be secured.
摘要翻译：一种用于显微平滑由具有低电阻率的硅单晶制成的晶片的表面的方法。在该方法中，使用HF和H2的混合气体在小于100℃的温度下除去在通过普通镜面抛光工艺抛光的晶片的表面上生长的自然氧化膜，然后用有机使用HCl和H2的混合气体在小于800℃的温度下除去沉积的物质。在一致的H2气氛中抑制氧化膜的再生长，在此期间晶片的表面粗糙度基本上不变化。然后将晶片在不低于800℃且小于1000℃的H 2气体气氛中进行热处理。蚀刻硅单晶衬底的工艺和由分解所形成的硅原子沉积的工艺产生的硅烷化合物被竞争地进行，从而软化晶片的微观粗糙表面，并提高镜面抛光表面的平滑度上的平滑度。由于将所有工艺温度设定为小于1000℃，因此能够抑制晶片中杂质的蒸发，能够确保低电阻率。

18. 发明授权

US5749974A Method of chemical vapor deposition and reactor therefor 失效
标题翻译：化学气相沉积方法及其反应器
公开(公告)号：US5749974A
公开(公告)日：1998-05-12
申请号：US502042
申请日：1995-07-13
申请人： Hitoshi Habuka , Masanori Mayuzumi , Naoto Tate , Masatake Katayama
发明人： Hitoshi Habuka , Masanori Mayuzumi , Naoto Tate , Masatake Katayama
IPC分类号： C23C16/44 , C23C16/455 , C30B25/08 , C30B25/14 , H01L21/205 , C23C16/00
CPC分类号： C30B25/08 , C23C16/455 , C30B25/14
摘要： A reactor for chemical vapor deposition which is capable of producing semiconductor crystalline thin films having small transition widths. The reactor includes a cold-wall type reaction chamber that is equipped with a gas inlet at one end and a gas outlet at the other end and a semiconductor substrate support which supports a semiconductor substrate so that a main surface thereof is horizontal. A reactant gas is caused to flow horizontally through the reaction chamber to effect the growing of a crystalline thin film on the main surface of the semiconductor substrate. The semiconductor substrate is arranged within the reactor chamber within a distance W which is measured from a leading edge of the semiconductor substrate at a most upstream position along a direction toward the gas outlet where W indicates an internal width of the reaction chamber. The semiconductor substrate is also in a location having a W/G ratio of 15 or greater, where G represents a distance between the main surface of the semiconductor substrate and a ceiling of the reaction chamber.
摘要翻译：一种用于化学气相沉积的反应器，其能够产生具有小转变宽度的半导体晶体薄膜。该反应器包括：冷壁式反应室，其在一端装有气体入口，另一端装有气体出口;以及半导体衬底支撑件，其支撑半导体衬底以使其主表面是水平的。使反应气体水平地流过反应室，以在半导体衬底的主表面上生长晶体薄膜。将半导体衬底布置在反应器室内的距离W内，该距离W是沿着朝向气体出口的方向的最上游位置从半导体衬底的前缘测量的，其中W表示反应室的内部宽度。半导体衬底也处于W / G比为15或更大的位置，其中G表示半导体衬底的主表面和反应室的顶部之间的距离。

19. 发明授权

US5427052A Method and apparatus for production of extremely thin SOI film substrate 失效
标题翻译：生产极薄SOI薄膜基板的方法和装置
公开(公告)号：US5427052A
公开(公告)日：1995-06-27
申请号：US873751
申请日：1992-04-27
申请人： Yutaka Ohta , Masatake Nakano , Masatake Katayama , Takao Abe
发明人： Yutaka Ohta , Masatake Nakano , Masatake Katayama , Takao Abe
IPC分类号： H01L21/302 , G01B11/06 , H01L21/3065 , H01L21/66 , H01L21/762 , H01L27/12 , C30B25/16
CPC分类号： H01L21/76251 , G01B11/0683 , H01L21/3065 , H01L22/12 , H01L22/20
摘要： A method and apparatus for uniformizing a bonded SOI (silicon on insulator) thin film layer by the reaction of chemical vapor-phase corrosion excited by the ultraviolet light, which effect the measurement of film thickness efficiently and conveniently and consequently attaining highly accurate control of the dispersion of thickness of the thin film layer without requiring the substrate to be removed from the reaction vessel for chemical vapor-phase corrosion on each occasion of the measurement or necessitating installation of a mechanism for alteration of the position of measurement inside or outside the reaction vessel are disclosed. The measurement of film thickness is carried out by keeping observation of interference fringes due to distribution of thickness of the film layer.
摘要翻译：通过由紫外光激发的化学气相腐蚀的反应使接合的SOI（绝缘体上硅）层均匀化的方法和装置，其有效和方便地实现膜厚度的测量，从而实现对在每次测量时，不需要从用于化学气相腐蚀的反应容器中除去衬底的薄膜层的厚度分散，或者需要安装用于改变反应容器内部或外部的测量位置的机构被披露。通过保持观察由于膜层的厚度分布引起的干涉条纹来进行膜厚度的测量。

20. 发明授权

US5171708A Method of boron diffusion into semiconductor wafers having reduced stacking faults 失效
标题翻译：硼原子扩散到具有减少的堆叠不良的半导体波长的方法
公开(公告)号：US5171708A
公开(公告)日：1992-12-15
申请号：US736546
申请日：1991-07-26
申请人： Masatake Katayama , Shoichi Fujiya , Isao Moroga , Masaru Shinomiya
发明人： Masatake Katayama , Shoichi Fujiya , Isao Moroga , Masaru Shinomiya
IPC分类号： H01L21/225
CPC分类号： H01L21/2254 , Y10S148/037 , Y10S438/909 , Y10S438/92
摘要： A method of diffusing boron into semiconductor wafers is disclosed which essentially includes boron deposition and boron diffusion. The deposition is performed from 900.degree. to 1,000.degree. C. and the diffusion at a temperature of 890.degree. to 1000.degree. C. Oxidation induced stacking faults are greatly reduced.

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