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11. 发明授权

US5401357A Dry etching method 失效
标题翻译：干蚀刻法
公开(公告)号：US5401357A
公开(公告)日：1995-03-28
申请号：US937781
申请日：1992-09-01
申请人： Hidekazu Okuhira , Tetsuo Ono , Susumu Hiraoka , Keizo Suzuki , Junji Shigeta , Hiroshi Masuda , Mitsuhiro Mori , Takuma Tanimoto , Shinichi Nakatsuka , Katsuhiko Mitani
发明人： Hidekazu Okuhira , Tetsuo Ono , Susumu Hiraoka , Keizo Suzuki , Junji Shigeta , Hiroshi Masuda , Mitsuhiro Mori , Takuma Tanimoto , Shinichi Nakatsuka , Katsuhiko Mitani
IPC分类号： H01L21/205 , H01L21/285 , H01L21/302 , H01L21/306 , H01L21/3065 , H01L21/308 , H01L21/316 , H01L21/331 , H01L21/335 , H01L21/338 , H01L29/205 , H01L29/73 , H01L29/737 , H01L29/778 , H01L29/812 , B44C1/22
CPC分类号： H01L29/66318 , H01L21/28587 , H01L21/30621 , H01L21/3081 , H01L21/31654 , H01L29/66462
摘要： A method may be used to dry etch a sample including a plurality of regions different from each other in the photo-absorption of a light having a specified wavelength using an etching gas plasma. The method is capable of selectively etching the desired material from a plurality of materials having different types of band gap energies or from a plurality of materials having different band gap energies. The method includes a step of irradiating a light having the specified wavelength on the sample for reducing an etching rate of a region having a large photo-absorption coefficient to the light, thereby selectively etching a region having a small photo-absorption coefficient to the light.
摘要翻译：在使用蚀刻气体等离子体对具有特定波长的光的光吸收中，可以使用一种方法来干蚀刻包括彼此不同的多个区域的样品。该方法能够从具有不同类型的带隙能量的多种材料或具有不同带隙能量的多种材料中选择性地蚀刻所需的材料。该方法包括在样品上照射具有特定波长的光以降低对光具有大的光吸收系数的区域的蚀刻速率的步骤，从而选择性地将具有小的光吸收系数的区域蚀刻到光。

12. 发明申请

US20070274144A1 Semiconductor Integrated Circuit Device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070274144A1
公开(公告)日：2007-11-29
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译：在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成比较器CP连接到预充电到高电压的匹配线HMLr。此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

13. 发明授权

US07228377B2 Semiconductor integrated circuit device, IC card, and mobile terminal 有权
标题翻译：半导体集成电路器件，IC卡和移动终端
公开(公告)号：US07228377B2
公开(公告)日：2007-06-05
申请号：US10857888
申请日：2004-06-02
申请人： Takanori Yamazoe , Takashi Tase , Junji Shigeta , Nobutaka Nagasaki , Eiji Yamasaki , Nobuhiro Oodaira , Kozo Katayama
发明人： Takanori Yamazoe , Takashi Tase , Junji Shigeta , Nobutaka Nagasaki , Eiji Yamasaki , Nobuhiro Oodaira , Kozo Katayama
IPC分类号： G06F12/00
CPC分类号： G06K19/077 , G06F12/0893 , G06F2212/2022 , G11C16/04 , G11C16/0466 , G11C16/102 , G11C16/105 , H01L27/115 , H01L27/11568
摘要： In a semiconductor integrated circuit device equipped with a flash memory and an EEPROM which are nonvolatile memories, the invention provides a technique that makes it possible to restrict an EEPROM capacity to a minimum necessary amount and reduce a chip area. Data of a minimal size required for one application program and rewritten frequently is stored in the EEPROM, and the EEPROM is configured to have a capacity of about that minimal size. Data of the same size that are respectively handled by other applications and rewritten frequently are stored in the flash memory. With respect to an application that is actually used, its data stored in the flash memory is transferred to the EEPROM and used. Data transfer between the flash memory and the EEPROM is performed if necessary. Consequently, the EEPROM capacity can be reduced and chip area reduction can be achieved.
摘要翻译：本发明提供了一种能够将EEPROM容量限制在最小必需量并减少芯片面积的技术，其中配备有闪存和EEPROM的半导体集成电路装置是非易失性存储器。一个应用程序所需的最小尺寸数据和频繁重写的数据存储在EEPROM中，并且EEPROM被配置为具有大约最小尺寸的容量。由其他应用程序分别处理并经常重写的相同大小的数据被存储在闪速存储器中。对于实际使用的应用，存储在闪速存储器中的数据被传送到EEPROM并使用。必要时，执行闪速存储器与EEPROM之间的数据传输。因此，可以减小EEPROM容量并且可以实现芯片面积的减小。

14. 发明授权

US07136595B2 Optical transmitter, optical receiver, and manufacturing method of optical device 有权
标题翻译：光发射机，光接收机，光学装置的制造方法
公开(公告)号：US07136595B2
公开(公告)日：2006-11-14
申请号：US10083617
申请日：2002-02-27
申请人： Masahiro Aoki , Junji Shigeta
发明人： Masahiro Aoki , Junji Shigeta
IPC分类号： H04B10/04
CPC分类号： G02F1/0356 , G02F1/0316 , H04B10/40
摘要： An optical transmitter-receiver is provided which is suitable for a high-speed optical communication system. A high-frequency electric line on a mounting substrate becomes a traveling-wave electrode of a semiconductor optical element equivalently by the following steps: separately manufacturing the mounting substrate having the high-frequency electric line, and the semiconductor optical element for which high-frequency design has been applied beforehand; and then bonding and mounting of drive electrodes of the mounting substrate and the semiconductor optical element through a soldering material. In addition, it is also possible to have a configuration in which not only junction down mounting of high-frequency semiconductor optical elements, but also that of an electronic element for electrically driving and controlling a light source such as a semiconductor laser and for electrically driving and controlling a high-frequency semiconductor optical element, is performed on the mounting substrate.
摘要翻译：提供适用于高速光通信系统的光收发器。安装基板上的高频电线通过以下步骤等效地成为半导体光学元件的行波电极：分别制造具有高频电线的安装基板和高频电路的半导体光学元件设计已被应用; 然后通过焊接材料将安装基板和半导体光学元件的驱动电极接合和安装。此外，还可以具有这样的结构，其不仅是高频半导体光学元件的结合安装，而且还可以是用于电驱动和控制诸如半导体激光器的光源和用于电驱动的电子元件并对安装基板进行高频半导体光学元件的控制。

15. 发明授权

US5523593A Compound semiconductor integrated circuit and optical regenerative repeater using the same 失效
标题翻译：复合半导体集成电路和使用其的光学再生中继器
公开(公告)号：US5523593A
公开(公告)日：1996-06-04
申请号：US36787
申请日：1993-03-25
申请人： Osamu Kagaya , Hiroyuki Takazawa , Yoshinori Imamura , Junji Shigeta , Yukihiro Kawata , Hiroto Oda
发明人： Osamu Kagaya , Hiroyuki Takazawa , Yoshinori Imamura , Junji Shigeta , Yukihiro Kawata , Hiroto Oda
IPC分类号： H01L27/06 , H01L29/08 , H01L29/778 , H01L31/0352
CPC分类号： H01L27/0605 , H01L29/0891
摘要： By forming an isolated semiconductor layer or electrode layer on a semiconductor surface between neighboring field effect transistors and element separating trenches which are deep enough to reach at least the semi-insulating substrate or the hetero junction interface on the buffer layer, low frequency oscillation of a compound semiconductor integrated circuit can be reduced. By controlling the thickness of the buffer layer having a hetero junction to at most 150 nm, the low frequency oscillation can be reduced. By forming materials separating adjacent elements with a width of at most 2 .mu.m which reach from the element region surface to the buffer layer having hetero junction so as to enclose the element regions and etched regions in the neighborhood of the elements or so as to enclose the element regions in the etched regions and by controlling the angle of the sides of the etched regions against the semiconductor layer surface to 10.degree. to 60.degree., wires can be prevented from short-circuiting.
摘要翻译：通过在相邻的场效应晶体管和元件分离沟槽之间的半导体表面上形成隔离的半导体层或电极层，该沟槽深度足以到达缓冲层上的至少半绝缘衬底或异质结界面，可以减少复合半导体集成电路。通过将具有异质结的缓冲层的厚度控制为至多150nm，可以降低低频振荡。通过形成将从元件区域表面到达具有异质结的缓冲层到达的至多2μm的宽度的相邻元件分开形成材料，以便在元件附近包围元件区域和蚀刻区域，以便包围蚀刻区域中的元件区域和通过将蚀刻区域的侧面相对于半导体层表面的角度控制在10°至60°，可以防止导线短路。

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