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    • 11. 发明申请
    • THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
    • 薄膜晶体管阵列及其制造方法
    • US20080003728A1
    • 2008-01-03
    • US11619407
    • 2007-01-03
    • Tae-Hyung HWANGHyung-Il JEONNam-Seok ROHSang-Il KIM
    • Tae-Hyung HWANGHyung-Il JEONNam-Seok ROHSang-Il KIM
    • H01L21/84
    • H01L27/124H01L27/12H01L27/1214H01L27/1218H01L27/1288H01L29/78603
    • A thin film transistor array panel and a method of manufacturing the same include: forming a gate electrode on an insulating substrate; sequentially forming a gate insulating layer; a semiconductor material layer and an ohmic contact material layer on the gate electrode; forming a first semiconductor layer pattern and a first ohmic contact pattern for covering the gate electrode and a surrounding area of the gate electrode by patterning the semiconductor material layer and the ohmic contact material layer; forming a conductive film on the gate insulating layer and the first ohmic contact pattern; forming a conductive film pattern on a partial area of the first ohmic contact pattern and a data line on the gate insulating layer by patterning the conductive film; forming a second ohmic contact pattern and a second semiconductor layer pattern by sequentially etching the first ohmic contact pattern and the first semiconductor layer pattern exposed by deviating from the conductive film pattern; forming a source electrode and a drain electrode separated from each other by patterning the conductive film pattern; forming an ohmic contact by etching the second ohmic contact pattern exposed between the separated source electrode and drain electrode; and forming a pixel electrode connected to the drain electrode. Therefore, even if an insulating substrate expands due to heat, erroneous alignment is not generated between a projection of the semiconductor layer and the source electrode and the drain electrode, thereby improving manufacturing efficiency and performance of a thin film transistor array panel.
    • 薄膜晶体管阵列面板及其制造方法包括:在绝缘基板上形成栅电极; 依次形成栅极绝缘层; 栅电极上的半导体材料层和欧姆接触材料层; 通过图案化所述半导体材料层和所述欧姆接触材料层,形成第一半导体层图案和第一欧姆接触图案,以覆盖所述栅电极和所述栅电极的周围区域; 在所述栅极绝缘层和所述第一欧姆接触图案上形成导电膜; 通过图案化导电膜,在第一欧姆接触图案的部分区域和栅极绝缘层上的数据线上形成导电膜图案; 通过依次蚀刻通过偏离导电膜图案而暴露的第一欧姆接触图案和第一半导体层图案,形成第二欧姆接触图案和第二半导体层图案; 通过图案化所述导电膜图案来形成彼此分离的源电极和漏电极; 通过蚀刻暴露在分离的源电极和漏极之间的第二欧姆接触图形来形成欧姆接触; 以及形成连接到所述漏电极的像素电极。 因此,即使绝缘基板由于热而膨胀,也不会在半导体层的突起与源电极和漏电极之间产生错误对准,从而提高薄膜晶体管阵列面板的制造效率和性能。
    • 12. 发明申请
    • ELECTROWETTING DISPLAY DEVICE
    • 电镀显示装置
    • US20130242367A1
    • 2013-09-19
    • US13595717
    • 2012-08-27
    • Hyeon-Gu CHOSang-Il KIMSeung-Jin BAEKJin-Woo CHOI
    • Hyeon-Gu CHOSang-Il KIMSeung-Jin BAEKJin-Woo CHOI
    • G02B26/02G02B26/00
    • G02B26/005
    • An electrowetting display device includes a first substrate, a second substrate, a conductive fluid and a non-conductive fluid. The first substrate includes a first base substrate, a first electrode layer, a hydrophobic insulation layer and a partition wall. The first electrode layer is formed on the first base substrate and includes pixel electrodes spaced apart from each other and a common notch electrode formed between the pixel electrodes. The hydrophobic insulation layer is formed on the first electrode layer. The partition wall is formed surrounding the pixel electrodes and the common notch electrode on the hydrophobic insulation layer. The second substrate is opposite to the first substrate. The conductive fluid and the non-conductive fluid are interposed between the first and second substrates. The conductive fluid and the non-conductive fluid are controlled to vary transmittance of light in accordance with an electric signal applied to the pixel electrodes.
    • 电润湿显示装置包括第一基板,第二基板,导电流体和非导电流体。 第一基板包括第一基底基板,第一电极层,疏水绝缘层和分隔壁。 第一电极层形成在第一基底基板上,并且包括彼此间隔开的像素电极和形成在像素电极之间的公共陷波电极。 疏水性绝缘层形成在第一电极层上。 围绕像素电极和疏水性绝缘层上的公共缺口电极形成分隔壁。 第二基板与第一基板相对。 导电流体和非导电流体介于第一和第二基板之间。 控制导电流体和非导电流体以根据施加到像素电极的电信号来改变光的透射率。
    • 13. 发明申请
    • DISPLAY DEVICE
    • 显示设备
    • US20100232009A1
    • 2010-09-16
    • US12783997
    • 2010-05-20
    • Sang-Il KIMNam-Seok ROHCheol-Woo PARKKyu-Young KIM
    • Sang-Il KIMNam-Seok ROHCheol-Woo PARKKyu-Young KIM
    • G02F1/167
    • G02F1/167G02F1/133512G02F1/134363G02F2001/1676G02F2001/1678
    • An electrophoretic display includes a lower substrate, an upper substrate, a color display layer on the lower substrate, a pixel electrode on the lower substrate, and a common electrode on the lower substrate or the upper substrate. The common electrode does not overlap the pixel electrode, and an electrophoretic active layer having a dispersion medium and electrophoretic particles is arranged between the lower substrate and the upper substrate. The electrophoretic active layer is a single-polarity electrophoretic particle system, and grayscales are generated depending on the number of electrophoretic particles arranged in a portion of the electrophoretic active layer corresponding to the pixel electrode. The position of the electrophoretic particles is controlled by the magnitude of the electric field applied between the pixel electrode and the common electrode.
    • 电泳显示器包括下基板,上基板,下基板上的彩色显示层,下基板上的像素电极,以及下基板或上基板上的公共电极。 公共电极不与像素电极重叠,并且具有分散介质和电泳粒子的电泳有源层布置在下基板和上基板之间。 电泳有源层是单极性电泳粒子系统,根据配置在与像素电极对应的电泳有源层的一部分中的电泳粒子的数量,产生灰度。 电泳粒子的位置由施加在像素电极和公共电极之间的电场的大小来控制。
    • 15. 发明申请
    • TRANSISTOR ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME
    • 晶体管阵列基板及其制造方法
    • US20080157101A1
    • 2008-07-03
    • US11955528
    • 2007-12-13
    • Tae-Hyung HWANGSeong-Sik SHINNam-Seok ROHSang-Il KIM
    • Tae-Hyung HWANGSeong-Sik SHINNam-Seok ROHSang-Il KIM
    • H01L33/00
    • H01L27/1266H01L27/1214H01L27/1288
    • A transistor array substrate includes a first substrate including a pixel region and a transistor region. The pixel region includes a pixel electrode, a portion of a disconnected gate line and a portion of a disconnected data line. The transistor region includes first and second gate connecting portions respectively connected to disconnected portions of the gate line, and first and second data connecting portions respectively connected to disconnected portions of the data line. The transistor array substrate also includes a second substrate including a gate line connecting portion connected to the first and second gate connecting portions, a data line connecting portion connecting the first and second data connecting portions, and a transistor connected to the gate line connecting portion, the data line connecting portion and the pixel electrode. The second substrate is attached to the transistor region of the first substrate.
    • 晶体管阵列基板包括包括像素区域和晶体管区域的第一基板。 像素区域包括像素电极,断开的栅极线的一部分和断开的数据线的一部分。 晶体管区域包括分别连接到栅极线的断开部分的第一和第二栅极连接部分,以及分别连接到数据线的断开部分的第一和第二数据连接部分。 晶体管阵列基板还包括第二基板,包括连接到第一和第二栅极连接部分的栅极线连接部分,连接第一和第二数据连接部分的数据线连接部分和连接到栅极线连接部分的晶体管, 数据线连接部分和像素电极。 第二衬底附接到第一衬底的晶体管区域。