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11. 发明授权

US07576582B2 Low-power clock gating circuit 有权
标题翻译：低功耗时钟门控电路
公开(公告)号：US07576582B2
公开(公告)日：2009-08-18
申请号：US11945387
申请日：2007-11-27
申请人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
发明人： Dae Woo Lee , Yil Suk Yang , Ik Jae Chun , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
IPC分类号： H03K3/289
CPC分类号： H03K3/0375
摘要： Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced in a sleep mode, and supply of a clock to a unused device of a targeted logic circuit is prevented by the control of a clock enable signal in an active mode, thereby reducing power consumption. The low-power clock gating circuit using an MTCMOS technique uses devices having a low threshold voltage and devices having a high threshold voltage, which makes it possible to implement a high-speed, low-power circuit, unlike a conventional clock gating circuit using a single threshold voltage.
摘要翻译：提供了使用多阈值CMOS（MTCMOS）技术的低功率时钟选通电路。低功率时钟选通电路包括输入级的锁存电路和输出级的与门电路，其中由休眠模式中的时钟门控电路中的漏电流引起的功耗降低，并且提供时钟通过控制活动模式中的时钟使能信号来防止目标逻辑电路的未使用的装置，从而降低功耗。使用MTCMOS技术的低功率时钟选通电路使用具有低阈值电压的器件和具有高阈值电压的器件，这使得可以实现高速，低功率电路，这与使用单阈值电压。

12. 发明授权

US08150903B2 Reconfigurable arithmetic unit and high-efficiency processor having the same 有权
标题翻译：可重构算术单元和具有相同功能的高效处理器
公开(公告)号：US08150903B2
公开(公告)日：2012-04-03
申请号：US12136107
申请日：2008-06-10
申请人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
发明人： Yil Suk Yang , Jung Hee Suk , Chun Gi Lyuh , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F7/57
CPC分类号： G06F7/57 , G06F7/5324 , G06F7/5338
摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.
摘要翻译：提供了一种可重构运算单元和具有该可重配置运算单元的处理器。可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

13. 发明申请

US20080291198A1 METHOD OF PERFORMING 3D GRAPHICS GEOMETRIC TRANSFORMATION USING PARALLEL PROCESSOR 审中-公开
标题翻译：使用并行处理器执行3D图形几何变换的方法
公开(公告)号：US20080291198A1
公开(公告)日：2008-11-27
申请号：US12100707
申请日：2008-04-10
申请人： Ik Jae Chun , Jung Hee Suk , Yil Suk Yang , Dae Woo Lee , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Jung Woo Lee
发明人： Ik Jae Chun , Jung Hee Suk , Yil Suk Yang , Dae Woo Lee , Tae Moon Roh , Jong Dae Kim , Ki Chul Kim , Jung Woo Lee
IPC分类号： G06T15/00
CPC分类号： G06T15/005 , G06T2210/52
摘要： Provided is a method of performing three-dimensional (3D) graphics geometric transformation using a parallel processor having a plurality of Processing Elements (PEs). The method includes performing model/view transformation and projection transformation on a first group of vertex vectors using the parallel processor; calculating a value used for quaternion correction of the first group of vertex vectors using a general-use processor, and simultaneously performing model/view transformation and projection transformation on a second group of vertex vectors; performing quaternion correction and screen mapping on the first group of vertex vectors, and simultaneously calculating a value used for quaternion correction of the second group of vertex vectors using the general-use processor; and performing quaternion correction and screen mapping on the second group of vertex vectors.
摘要翻译：提供了一种使用具有多个处理元件（PE）的并行处理器执行三维（3D）图形几何变换的方法。该方法包括使用并行处理器对第一组顶点向量执行模型/视图变换和投影变换; 使用通用处理器计算用于第一组顶点矢量的四元数校正的值，并且同时对第二组顶点矢量执行模型/视图变换和投影变换; 对所述第一组顶点向量进行四元数校正和画面映射，并且使用所述通用处理器同时计算用于所述第二组顶点向量的四元数校正的值; 并对第二组顶点向量执行四元数校正和屏幕映射。

14. 发明申请

US20080133879A1 SIMD parallel processor with SIMD/SISD/row/column operation modes 审中-公开
标题翻译： SIMD并行处理器采用SIMD / SISD /行/列操作模式
公开(公告)号：US20080133879A1
公开(公告)日：2008-06-05
申请号：US11906381
申请日：2007-10-01
申请人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim , Chun Gi Lyuh
发明人： Yil Suk Yang , Tae Moon Roh , Dae Woo Lee , Jong Dae Kim , Chun Gi Lyuh
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/30036 , G06F9/30098 , G06F9/3012 , G06F9/30123 , G06F9/30141 , G06F9/30181 , G06F9/30189
摘要： Provided is a single instruction multiple data (SIMD) parallel processor including a plurality of processing units connected to one another. Each processing unit includes: an instruction register; an instruction decoder; a register files selection circuit; and register files. The SIMD parallel processor can selectively control data of register files required for any one of SIMD, single instruction single data (SISD), row, and column operations in response to an instruction. Since each of the SIMD, SISD, row, and column operations can be effectively performed according to the type of application, the SIMD parallel processor has excellent utility, efficiency, and flexibility.
摘要翻译：提供了包括彼此连接的多个处理单元的单指令多数据（SIMD）并行处理器。每个处理单元包括：指令寄存器; 指令解码器; 寄存器文件选择电路; 并注册文件。 SIMD并行处理器可以选择性地控制响应于指令的SIMD，单指令单数据（SISD），行和列操作中的任何一个所需的寄存器文件的数据。由于可以根据应用类型有效地执行SIMD，SISD，行和列操作，所以SIMD并行处理器具有优异的效用，效率和灵活性。

15. 发明授权

US07958179B2 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US07958179B2
公开(公告)日：2011-06-07
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F7/38
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从ALU，乘法器和移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

16. 发明申请

US20080140745A1 Arithmetic method and device of reconfigurable processor 失效
标题翻译：可重构处理器的算术方法和装置
公开(公告)号：US20080140745A1
公开(公告)日：2008-06-12
申请号：US11978878
申请日：2007-10-30
申请人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
发明人： Chun Gi Lyuh , Soon Il Yeo , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F5/01
CPC分类号： G06F7/57
摘要： Provided are an arithmetic method and device of a reconfigurable processor. The arithmetic device includes: an Arithmetic Logic Unit (ALU) for performing an addition and subtraction operation and a logic operation of a binary signal; a multiplier for performing a multiplication operation of the binary signal; a shifter for changing an arrangement of the binary signal; a first operand selector and a second operand selector each for selecting one of values output from the ALU, the multiplier, and the shifter; and an adder for adding the values selected by the first operand selector and the second operand selector.
摘要翻译：提供了可重构处理器的算术方法和装置。算术装置包括：用于执行加法运算和减法运算的算术逻辑单元（ALU）和二进制信号的逻辑运算; 用于执行二进制信号的乘法运算的乘法器; 用于改变二进制信号的布置的移位器; 每个用于选择从所述ALU，所述乘法器和所述移位器输出的值之一的第一操作数选择器和第二操作数选择器; 以及用于将由第一操作数选择器和第二操作数选择器选择的值相加的加法器。

17. 发明授权

US09391462B2 Energy storage system with wired and wireless energy transfer function 有权
标题翻译：储能系统具有有线和无线能量传递功能
公开(公告)号：US09391462B2
公开(公告)日：2016-07-12
申请号：US13596618
申请日：2012-08-28
申请人： Yil Suk Yang , Jong Dae Kim , Se Wan Heo , Ji Min Oh , Min Ki Kim , Jong Kee Kwon
发明人： Yil Suk Yang , Jong Dae Kim , Se Wan Heo , Ji Min Oh , Min Ki Kim , Jong Kee Kwon
IPC分类号： H01F27/42 , H02J5/00 , H02J7/00
CPC分类号： H02J50/00 , H02J5/005 , H02J7/0063 , H02J7/025
摘要： Disclosed is an energy storage system provided with a wired and wireless energy transfer function. The energy storage system includes: an energy input unit to which energy generated from a plurality of energy sources is input; an energy input control unit for selecting one energy source from among the plurality of energy sources, and transferring energy of the selected energy source through operation in a wired operation mode or a wireless operation mode; a wireless energy transmitting/receiving unit for wirelessly transmitting/receiving the energy of the selected energy source during the operation in the wireless operation mode of the energy input control unit; an energy storage/control unit for storing the energy of the selected energy source; an energy output unit for consuming the energy stored in the energy storage/control unit; and an energy output control unit for distributing the energy stored in the energy storage/control unit to the energy output unit.
摘要翻译：公开了一种具有有线和无线能量传递功能的能量存储系统。能量存储系统包括：输入从多个能量源产生的能量的能量输入单元; 能量输入控制单元，用于从所述多个能量源中选择一个能量源，并且通过在有线操作模式或无线操作模式中的操作来传送所选择的能量源的能量; 无线能量发送/接收单元，用于在能量输入控制单元的无线操作模式下的操作期间，无线地发送/接收所选择的能量源的能量; 用于存储所选能量源的能量的能量存储/控制单元; 用于消耗存储在能量存储/控制单元中的能量的能量输出单元; 以及能量输出控制单元，用于将存储在能量存储/控制单元中的能量分配给能量输出单元。

18. 发明申请

US20130193774A1 ENERGY STORAGE SYSTEM WITH WIRED AND WIRELESS ENERGY TRANSFER FUNCTION 有权
标题翻译：具有有线和无线能量传递功能的能源存储系统
公开(公告)号：US20130193774A1
公开(公告)日：2013-08-01
申请号：US13596618
申请日：2012-08-28
申请人： Yil Suk Yang , Jong Dae Kim , Se Wan Heo , Ji Min Oh , Min Ki Kim , Jong Kee Kwon
发明人： Yil Suk Yang , Jong Dae Kim , Se Wan Heo , Ji Min Oh , Min Ki Kim , Jong Kee Kwon
IPC分类号： H02J7/00
CPC分类号： H02J50/00 , H02J5/005 , H02J7/0063 , H02J7/025
摘要： Disclosed is an energy storage system provided with a wired and wireless energy transfer function. The energy storage system includes: an energy input unit to which energy generated from a plurality of energy sources is input; an energy input control unit for selecting one energy source from among the plurality of energy sources, and transferring energy of the selected energy source through operation in a wired operation mode or a wireless operation mode; a wireless energy transmitting/receiving unit for wirelessly transmitting/receiving the energy of the selected energy source during the operation in the wireless operation mode of the energy input control unit; an energy storage/control unit for storing the energy of the selected energy source; an energy output unit for consuming the energy stored in the energy storage/control unit; and an energy output control unit for distributing the energy stored in the energy storage/control unit to the energy output unit.
摘要翻译：公开了一种具有有线和无线能量传递功能的能量存储系统。能量存储系统包括：输入从多个能量源产生的能量的能量输入单元; 能量输入控制单元，用于从所述多个能量源中选择一个能量源，并且通过在有线操作模式或无线操作模式中的操作来传送所选择的能量源的能量; 无线能量发送/接收单元，用于在能量输入控制单元的无线操作模式下的操作期间，无线地发送/接收所选择的能量源的能量; 用于存储所选能量源的能量的能量存储/控制单元; 用于消耗存储在能量存储/控制单元中的能量的能量输出单元; 以及能量输出控制单元，用于将存储在能量存储/控制单元中的能量分配到能量输出单元。

19. 发明授权

US07721038B2 System on chip (SOC) system for a multimedia system enabling high-speed transfer of multimedia data and fast control of peripheral devices 有权
标题翻译：用于多媒体系统的片上系统（SOC）系统，可实现多媒体数据的高速传输和外围设备的快速控制
公开(公告)号：US07721038B2
公开(公告)日：2010-05-18
申请号：US12171397
申请日：2008-07-11
申请人： Ik Jae Chun , Tae Moon Roh , Jong Dae Kim
发明人： Ik Jae Chun , Tae Moon Roh , Jong Dae Kim
IPC分类号： G06F13/36 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1657 , G06F13/28
摘要： Provided is a System on Chip (SoC) system for a multimedia system enabling high-speed transfer of a large amount of multimedia data and a processor to rapidly control a peripheral device. The SoC system includes a processor; a plurality of peripheral devices; a plurality of physically divided memories; a control bus for transferring a control signal from the processor to the peripheral devices and the memories; a data bus for transferring data between the processor, the peripheral devices and the memories; a bridge for coupling the control bus and the data bus to the processor; a plurality of memory controllers coupled to the control bus and controlling each of the memories; a Direct Memory Access (DMA) controller coupled to the data bus and the control bus and controlling data transfer between the peripheral devices and the memories; and a matrix switch coupled between the DMA controller and the memory controllers and enabling simultaneous multiple memory access.
摘要翻译：提供了一种用于多媒体系统的片上系统（SoC）系统，能够高速传输大量的多媒体数据和处理器来快速控制外围设备。 SoC系统包括一个处理器; 多个外围设备; 多个物理划分的存储器; 用于将控制信号从处理器传送到外围设备和存储器的控制总线; 用于在处理器，外围设备和存储器之间传送数据的数据总线; 用于将控制总线和数据总线耦合到处理器的桥; 耦合到控制总线并控制每个存储器的多个存储器控制器; 耦合到数据总线和控制总线的直接存储器访问（DMA）控制器，并控制外围设备和存储器之间的数据传输; 以及耦合在DMA控制器和存储器控制器之间的矩阵开关，并且能够同时进行多个存储器访问。

20. 发明申请

US20070150763A1 Highly energy-efficient processor employing dynamic voltage scaling 有权
标题翻译：采用动态电压调节的高能效处理器
公开(公告)号：US20070150763A1
公开(公告)日：2007-06-28
申请号：US11520177
申请日：2006-09-13
申请人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
发明人： Yil Suk Yang , Jong Dae Kim , Soon Il Yeo , Chun Gi Lyuh
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3287 , G06F1/3293 , G06F1/3296 , Y02D10/122 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： Provided is a highly energy-efficient processor architecture. The architecture employs 2-stage dynamic voltage scaling (DVS) and a sleep mode for high energy efficiency, dynamically controls the power supply voltage and activation of an embedded processor with instructions, and thus can prevent performance deterioration while reducing power consumption.A highly energy-efficient processor employing the processor architecture includes: a function unit block for performing an operation according to instructions input from the outside; at least one peripheral unit block for performing data communication with an external device; an instruction decoder for interpreting the input instructions and determining operation modes of the function unit block and peripheral unit block required for executing the interpreted instructions; a function unit block driver for applying a different power supply voltage according to the operation mode of the function unit block to the function unit block; and a peripheral unit block driver for applying a different power supply voltage according to the operation mode of the peripheral unit block to the peripheral unit block.
摘要翻译：提供了一种高能效的处理器架构。该架构采用2级动态电压调节（DVS）和睡眠模式以实现高能效，通过指令动态控制电源电压和嵌入式处理器的激活，从而可以在降低功耗的同时防止性能下降。采用该处理器架构的高能效处理器包括：功能单元块，用于根据从外部输入的指令进行操作; 用于与外部设备进行数据通信的至少一个外围单元块; 用于解释输入指令并确定执行解释指令所需的功能单元块和外围单元块的操作模式的指令解码器; 功能单元块驱动器，用于根据功能单元块的操作模式将不同的电源电压施加到功能单元块; 以及外围单元块驱动器，用于根据外围单元块的操作模式向外围单元块施加不同的电源电压。

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