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11. 发明授权

US06529084B1 Interleaved feedforward VCO and PLL 有权
标题翻译：交错前馈VCO和PLL
公开(公告)号：US06529084B1
公开(公告)日：2003-03-04
申请号：US09974986
申请日：2001-10-11
申请人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03B524
CPC分类号： H03L7/0998 , H03K3/0315 , H03L7/0891 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.
摘要翻译：公开了一种允许低电压，高频，低抖动操作的压控振荡器（VCO）和锁相环（PLL）拓扑。传统的PLL设计被修改为将误差信号分成AC和DC分量。接受AC和DC分量控制输入的VCO根据两个输入调节其输出频率。

12. 发明授权

US06570408B2 Charge recovery for dynamic circuits 有权
标题翻译：动态电路充电恢复
公开(公告)号：US06570408B2
公开(公告)日：2003-05-27
申请号：US09931304
申请日：2001-08-16
申请人： Kevin John Nowka
发明人： Kevin John Nowka
IPC分类号： H03K19096
CPC分类号： H03K19/0019
摘要： In one aspect, a method for charge recovery in dynamic circuitry includes discharging a dynamic node during an evaluation interval by input circuitry coupled to the dynamic node responsive to one or more input signals. The discharging includes transferring the charge from the dynamic node to a capacitor during the evaluation time interval. The dynamic node is charged during a precharge interval by a voltage source and precharge timing circuitry coupled to the dynamic node responsive to a precharge signal. The charging includes transferring the charge from the capacitor back to the dynamic node.
摘要翻译：一方面，一种用于动态电路中的电荷恢复的方法包括：响应于一个或多个输入信号，通过耦合到动态节点的输入电路在评估间隔期间对动态节点进行放电。放电包括在评估时间间隔期间将电荷从动态节点转移到电容器。动态节点在预充电间隔期间被电压源充电，并且响应于预充电信号耦合到动态节点的预充电定时电路。充电包括将电荷从电容器转移回动态节点。

13. 发明授权

US06445217B1 Edge-triggered latch with balanced pass-transistor logic trigger 失效
标题翻译：边沿触发锁存器，具有平衡的传导晶体管逻辑触发
公开(公告)号：US06445217B1
公开(公告)日：2002-09-03
申请号：US09810026
申请日：2001-03-15
申请人： Nobuo Kojima , Kevin John Nowka , Huajun Wen
发明人： Nobuo Kojima , Kevin John Nowka , Huajun Wen
IPC分类号： H03F345
CPC分类号： H03K3/356156 , H03K3/037
摘要： An edge-triggered latch that incorporates pass-transistor logic (PTL) in the data and clock generation paths. In accordance with one embodiment, an edge-triggered latch includes a data input and at least one data path PTL transistor that passes data from the data input into a storage node in response to a latch trigger signal. A latch trigger circuit generates the latch-trigger signal in response to a clock signal transition.
摘要翻译：在数据和时钟产生路径中集成了通过晶体管逻辑（PTL）的边沿触发锁存器。根据一个实施例，边缘触发锁存器包括数据输入和至少一个数据通路PTL晶体管，其响应于锁存触发信号将数据从输入到存储节点的数据传送。锁存触发电路响应时钟信号转换产生锁存触发信号。

14. 发明授权

US06441667B1 Multiphase clock generator 失效
标题翻译：多相时钟发生器
公开(公告)号：US06441667B1
公开(公告)日：2002-08-27
申请号：US09820460
申请日：2001-03-29
申请人： David William Boerstler , Robert Keven Montoye , Kevin John Nowka
发明人： David William Boerstler , Robert Keven Montoye , Kevin John Nowka
IPC分类号： G06F104
CPC分类号： H03L7/087 , G06F1/04 , H03L7/091 , H03L7/0995 , Y10S331/02
摘要： The Sync State outputs are used in combination with the multiple phase outputs to generate and error signal which is operable to generate a control voltage which controls the frequency of the MVCO and to-generate a shifted clock which is divided in a sequential circuit to generate the quadrature clock with a frequency F.
摘要翻译：同步状态输出与多相输出组合使用以产生和误差信号，该信号可用于产生控制电压，该控制电压控制MVCO的频率并产生移位的时钟，该时钟被分成顺序电路以产生具有频率F的正交时钟

15. 发明授权

US06405231B1 Method and apparatus for rounding intermediate normalized mantissas within a floating-point processor 失效
标题翻译：在浮点处理器内舍入中间标准化尾数的方法和装置
公开(公告)号：US06405231B1
公开(公告)日：2002-06-11
申请号：US09282270
申请日：1999-03-31
申请人： Kevin John Nowka
发明人： Kevin John Nowka
IPC分类号： G06F738
CPC分类号： G06F7/49957
摘要： An apparatus for rounding intermediate normalized mantissas within a floating-point processor is disclosed. The apparatus for rounding intermediate normalized mantissas within a floating-point processor includes an AND circuit, a selection circuit, and a multiplexor. The AND circuit generates an AND signal and its complement from a normalized mantissa. The selection circuit generates a select_AND signal and its complement from the normalized mantissa. The multiplexor, which is coupled to the AND circuit and the selection circuit, chooses either the AND signal or its complement signal as a rounded normalized mantissa according to the select_AND signal and its complement signal from the selection circuit.
摘要翻译：公开了一种用于在浮点处理器内舍入中间标准化尾数的装置。用于对浮点处理器内的中间归一化尾数进行舍入的装置包括与电路，选择电路和多路复用器。 “与”电路从标准化尾数生成一个“与”信号及其补码。选择电路从标准化尾数生成一个select_AND信号及其补码。耦合到AND电路和选择电路的多路复用器根据来自选择电路的select_AND信号及其补码信号，选择AND信号或其补码信号作为舍入的归一化尾数。

16. 发明申请

US20090302894A1 DUAL GATE TRANSISTOR KEEPER DYNAMIC LOGIC 有权
标题翻译：双门晶体管保持器动态逻辑
公开(公告)号：US20090302894A1
公开(公告)日：2009-12-10
申请号：US11859351
申请日：2007-09-21
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
IPC分类号： H03K19/20 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a device for charging a dynamic node during a pre-charge phase of a clock. A logic tree evaluates the dynamic node with a device during an evaluate phase of the clock. The dynamic node has a keeper circuit comprising an inverter with its input coupled to the dynamic node and its output coupled to the back gate of a dual gate PFET device. The source of the dual gate PFET is coupled to the power supply and its drain is coupled to the dynamic node forming a half latch. The front gate of the dual gate PFET is coupled to a logic circuit with a mode input and a logic input coupled back to a node sensing the state of the dynamic node. The mode input may be a slow mode to preserve dynamic node state or the clock delayed that turns ON the strong keeper after evaluation.
摘要翻译：动态逻辑门具有用于在时钟的预充电阶段对动态节点充电的装置。逻辑树在时钟的评估阶段使用设备来评估动态节点。动态节点具有保持器电路，其包括反相器，其输入耦合到动态节点，其输出耦合到双栅极PFET器件的背栅极。双栅极PFET的源极耦合到电源，并且其漏极耦合到形成半锁存器的动态节点。双栅极PFET的前栅极耦合到具有模式输入和逻辑输入的逻辑电路，逻辑输入耦合回到感测动态节点的状态的节点。模式输入可能是缓慢的模式，以保持动态节点状态或时钟延迟，在评估后打开强守护者。

17. 发明授权

US07265589B2 Independent gate control logic circuitry 失效
标题翻译：独立门控逻辑电路
公开(公告)号：US07265589B2
公开(公告)日：2007-09-04
申请号：US11168717
申请日：2005-06-28
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Kevin John Nowka
IPC分类号： H03K19/20 , H03K19/094 , H03K19/00 , H03K19/096
CPC分类号： H03K19/0963
摘要： A dynamic logic gate has a dynamic node pre-charged in response to a pre-charge phase of a clock signal and a logic tree with a plurality of logic inputs for evaluating the dynamic node during an evaluate phase of the clock signal in response to a Boolean combination of the logic inputs. The logic tree has a stacked configuration with at least one multi-gate FEAT device for coupling an intermediate node of the logic tree to the dynamic node in response to a first logic input of the plurality of logic inputs or in response to the pre-charge phase of the clock signal. The multi-gate FEAT device has one gate coupled to the first logic input and a second gate coupled to a complement of the clock signal used to pre-charge the dynamic node.
摘要翻译：动态逻辑门具有响应于时钟信号的预充电阶段和具有多个逻辑输入的逻辑树预充电的动态节点，用于在响应于时钟信号的时钟信号的估计阶段期间评估动态节点逻辑输入的布尔组合。逻辑树具有堆叠配置，其具有至少一个多栅极FEAT装置，用于响应于多个逻辑输入的第一逻辑输入或响应于预充电而将逻辑树的中间节点耦合到动态节点时钟信号的相位。多栅极FEAT器件具有耦合到第一逻辑输入的一个栅极和耦合到用于对动态节点预充电的时钟信号的补码的第二栅极。

18. 发明授权

US06836849B2 Method and apparatus for controlling power and performance in a multiprocessing system according to customer level operational requirements 有权
标题翻译：根据客户级操作要求，在多处理系统中控制功率和性能的方法和装置
公开(公告)号：US06836849B2
公开(公告)日：2004-12-28
申请号：US09826986
申请日：2001-04-05
申请人： Bishop Chapman Brock , Harm Peter Hofstee , Mark A. Johnson , Thomas Walter Keller, Jr. , Kevin John Nowka
发明人： Bishop Chapman Brock , Harm Peter Hofstee , Mark A. Johnson , Thomas Walter Keller, Jr. , Kevin John Nowka
IPC分类号： G06F126
CPC分类号： G06F1/3203
摘要： A method and controller for managing power and performance of a multiprocessor (MP) system is described. The controller receives sensor data corresponding to physical parameters within the MP system. The controller also receives quality of service and policy parameters corresponding to the MP system. The quality of service parameters define commitments to customers for utilization of the MP system. The policy parameters correspond to operation limits on inputs and outputs of the MP system. The operation input limits relate to the cost and availability of power or individual processor availability. The operation output limits relate to the amount of heat, acoustic noise levels, EMC levels, etc. that the individual or group of processors in the MP system are allowed to generate in a particular environment. A controller receives the physical parameters, the quality of service parameters and policy parameters and determines performance goals for the MP system and processors within the MP system. Then controller generates controls and applies them to individual processors to achieve the performance goals.
摘要翻译：描述了一种用于管理多处理器（MP）系统的功率和性能的方法和控制器。控制器接收与MP系统内的物理参数对应的传感器数据。控制器还接收与MP系统对应的服务质量和策略参数。服务质量参数定义了对客户使用MP系统的承诺。策略参数对应于MP系统的输入和输出的操作限制。操作输入限制涉及功率或单个处理器可用性的成本和可用性。操作输出限制涉及允许MP系统中的个体或一组处理器在特定环境中生成的热量，声学噪声水平，EMC等级等。控制器接收物理参数，服务质量参数和策略参数，并确定MP系统中的MP系统和处理器的性能目标。然后控制器生成控件并将其应用于各个处理器以实现性能目标。

19. 发明授权

US06650163B1 Clock generator for integrated circuit 有权
标题翻译：时钟发生器用于集成电路
公开(公告)号：US06650163B1
公开(公告)日：2003-11-18
申请号：US10216618
申请日：2002-08-08
申请人： Jeffrey L. Burns , Alan James Drake , Uttam Shyamalindu Ghoshal , Kevin John Nowka
发明人： Jeffrey L. Burns , Alan James Drake , Uttam Shyamalindu Ghoshal , Kevin John Nowka
IPC分类号： H03K300
CPC分类号： H03B5/1212 , H03B5/1228 , H03K3/354
摘要： A system and integrated circuit (die) including a clock generator that includes an on-chip inductor and uses the inherent capacitance of the load to generate a sinusoidal clock signal. The inductor is connected between a current source and an inverting switch. The output of the switch is a substantially sinusoidal signal that connected directly to at least a portion of the clock driven circuits without intermediate buffering. In the preferred embodiment, the clock generator is a dual phase design that includes a pair of cross-coupled MOSFET's, a pair of solid state on-chip inductors, and a current source. Each of the on-chip inductors is connected between the current source and the drain of one of the MOSFET's. The outputs of the clock generator are provided directly to the clock inputs of at least a portion of the clock driven circuits on the die. In this embodiment, the frequency of the clock generator output signal is predominantly determined by the inductance of the inductive elements and the capacitance of the clock driven circuitry. This design eliminates the need for incorporating distinct capacitor elements in the clock generator itself and produces a clock generator in which a significant portion of the power oscillates between the generator's inductive elements and the capacitive elements of the load thereby reducing the power required to be supplied by the current source.
摘要翻译：一种包括时钟发生器的系统和集成电路（芯片），其包括片上电感器并且使用负载的固有电容来产生正弦时钟信号。电感连接在电流源和反相开关之间。开关的输出是基本上正弦信号，其直接连接到时钟驱动电路的至少一部分而没有中间缓冲。在优选实施例中，时钟发生器是双相设计，其包括一对交叉耦合MOSFET，一对固态片上电感器和电流源。每个片上电感器连接在MOSFET之一的电流源和漏极之间。时钟发生器的输出被直接提供给芯片上至少一部分时钟驱动电路的时钟输入。在该实施例中，时钟发生器输出信号的频率主要由电感元件的电感和时钟驱动电路的电容决定。该设计消除了在时钟发生器本身中并入不同的电容器元件并产生时钟发生器的需要，其中大部分功率在发电机的感应元件和负载的电容元件之间振荡，从而减少由当前来源。

20. 发明授权

US06529924B1 Method and apparatus for generating shift amount signals for an alignment shifter 失效
标题翻译：用于产生对准移位器的移位量信号的方法和装置
公开(公告)号：US06529924B1
公开(公告)日：2003-03-04
申请号：US09535525
申请日：2000-03-27
申请人： Kevin John Nowka
发明人： Kevin John Nowka
IPC分类号： G06F700
CPC分类号： G06F7/485 , G06F7/49936
摘要： A method for generating shift amount signals for an alignment shifter is disclosed. In a process of adding a first floating-point number and a second floating-point number, wherein the floating-point numbers includes a sign, a mantissa, and an exponent, an alignment shifter is used to provide proper alignment for the floating-point numbers. Residue arithmetics are performed on an exponent of the first floating-point number and an exponent of the second floating-point number to generate a residue shift amount. The residue shift amount is then decoded to obtain shift amount signals that are readable by the alignment shifter.
摘要翻译：公开了一种用于产生对准移位器的移位量信号的方法。在添加第一浮点数和第二浮点数的处理中，浮点数包括符号，尾数和指数，使用对准移位器为浮点数提供适当的对齐数字。残差算术以第一浮点数的指数和第二浮点数的指数执行，以产生残差移位量。然后将残留偏移量解码以获得可由对准移位器读取的移位量信号。

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