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11. 发明授权

US08862823B1 Compression status caching 有权
标题翻译：压缩状态缓存
公开(公告)号：US08862823B1
公开(公告)日：2014-10-14
申请号：US12340503
申请日：2008-12-19
申请人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
发明人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0897 , G06F12/0848 , G06F12/1009 , G06F12/123 , G06F2212/1041 , G06F2212/401 , G06F2212/455 , G06F2212/466 , G06T1/60
摘要： One embodiment of the present invention sets forth a compression status cache configured to store compression information for blocks of memory stored within an external memory. A data cache unit is configured to request, in response to a cache miss, compressed data from the external memory based on compression information stored in the compression status bit cache. The compression status for active buffers is dynamically swapped into the compression status cache as needed. Different compression formats may be specified for one or more tiles within an active buffer. One advantage of the disclosed compression status cache is that a lame amount of attached memory may be allocated as compressible memory blocks, without incurring a corresponding die area cost because a portion of the compression status stored off chip in attached memory is cached in the compression status cache.
摘要翻译：本发明的一个实施例提出了一种被配置为存储存储在外部存储器中的存储器块的压缩信息的压缩状态缓存。数据高速缓存单元被配置为基于存储在压缩状态位高速缓存中的压缩信息，响应于高速缓存未命中来请求来自外部存储器的压缩数据。活动缓冲区的压缩状态根据需要动态交换到压缩状态缓存。可以为活动缓冲区内的一个或多个瓦片指定不同的压缩格式。所公开的压缩状态高速缓存的一个优点是可以将大量附加存储器分配为可压缩存储器块，而不会引起相应的管芯区域成本，因为存储在附加存储器中的芯片外的存储器的一部分被缓存在压缩状态缓存。

12. 发明授权

US08504773B1 Storing dynamically sized buffers within a cache 有权
标题翻译：在缓存中存储动态大小的缓冲区
公开(公告)号：US08504773B1
公开(公告)日：2013-08-06
申请号：US12326764
申请日：2008-12-02
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G06F9/46
CPC分类号： G06F15/167
摘要： A system and method for buffering intermediate data in a processing pipeline architecture stores the intermediate data in a shared cache that is coupled between one or more pipeline processing units and an external memory. The shared cache provides storage that is used by multiple pipeline processing units. The storage capacity of the shared cache is dynamically allocated to the different pipeline processing units as needed, to avoid stalling the upstream units, thereby improving overall system throughput.
摘要翻译：用于缓冲处理流水线架构中的中间数据的系统和方法将中间数据存储在耦合在一个或多个流水线处理单元和外部存储器之间的共享高速缓存中。共享缓存提供多个流水线处理单元使用的存储。共享缓存的存储容量根据需要动态分配给不同的流水线处理单元，以避免停止上游单元，从而提高整体系统吞吐量。

13. 发明授权

US08271734B1 Method and system for converting data formats using a shared cache coupled between clients and an external memory 有权
标题翻译：使用在客户机和外部存储器之间耦合的共享缓存来转换数据格式的方法和系统
公开(公告)号：US08271734B1
公开(公告)日：2012-09-18
申请号：US12329345
申请日：2008-12-05
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F13/00
CPC分类号： G06F12/084 , G06F2212/401
摘要： A system and method for converting data from one format to another in a processing pipeline architecture. Data is stored in a shared cache that is coupled between one or more clients and an external memory. The shared cache provides storage that is used by multiple clients rather than being dedicated to separately convert the data format for each client. Each client may interface with the memory using a different format, such as a compressed data format. Data is converted to the format expected by the particular client as it is read from the cache and output to the client during a read operation. Bytes of a cache line may be remapped to bytes of an unpack register for output to a naïve client, which may be configured to perform texture mapping operations. Data is converted from the client format to the memory format as it is stored into the cache during a write operation.
摘要翻译：一种用于在处理流水线架构中将数据从一种格式转换为另一种格式的系统和方法。数据存储在耦合在一个或多个客户端和外部存储器之间的共享高速缓存中。共享缓存提供由多个客户端使用的存储，而不是专用于分别转换每个客户端的数据格式。每个客户端可以使用不同的格式（例如压缩数据格式）与存储器接口。在读取操作期间，数据将从特定客户端转换为预期的格式，并从缓存中读取并输出到客户端。高速缓存行的字节可以重新映射到解包寄存器的字节，以输出到初始客户机，其可以被配置为执行纹理映射操作。数据从客户端格式转换为存储格式，因为它在写操作期间存储到高速缓存中。

14. 发明授权

US08868838B1 Multi-class data cache policies 有权
标题翻译：多类数据缓存策略
公开(公告)号：US08868838B1
公开(公告)日：2014-10-21
申请号：US12276154
申请日：2008-11-21
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts
IPC分类号： G06F12/12
CPC分类号： G06F12/126
摘要： One embodiment of the invention sets forth a mechanism for evicting data from a data cache based on the data class of that data. The data stored in the cache lines in the data cache is categorized based on data classes that reflect the reuse potential of that data. The data classes are stored in a tag store, where each tag within the tag store corresponds to a single cache line within the data cache. When reserving a cache line for the data associated with a command, a tag look-up unit examines the data classes in the tag store to determine which data to evict. Data that has a low reuse potential is evicted at a higher priority than data that has a high reuse potential. Advantageously, evicting data that belongs to a data class that has a lower reuse potential reduces the number of cache misses within the system.
摘要翻译：本发明的一个实施例提出了一种基于该数据的数据类从数据高速缓存中取出数据的机制。存储在数据高速缓存中的高速缓存行中的数据基于反映该数据的重用潜力的数据类进行分类。数据类存储在标签存储中，其中标签存储中的每个标签对应于数据高速缓存内的单个高速缓存行。当为与命令相关联的数据保留高速缓存行时，标签查找单元检查标签存储中的数据类以确定要驱逐的数据。具有较低重用潜力的数据的优先级高于具有高重用潜力的数据。有利地，驱逐属于具有较低再利用潜力的数据类的数据减少了系统内的高速缓存未命中的数量。

15. 发明授权

US08874844B1 Padding buffer requests to avoid reads of invalid data 有权
标题翻译：填充缓冲区请求以避免读取无效数据
公开(公告)号：US08874844B1
公开(公告)日：2014-10-28
申请号：US12326760
申请日：2008-12-02
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0802 , G06F12/0862 , G06Q10/06311
摘要： A system and method for buffering intermediate data in a processing pipeline architecture stores the intermediate data in a shared cache that is coupled between one or more pipeline processing units and an external memory. The shared cache provides storage that is used by multiple pipeline processing units. The storage capacity of the shared cache is dynamically allocated to the different pipeline processing units as needed, to avoid stalling the upstream units, thereby improving overall system throughput.
摘要翻译：用于缓冲处理流水线架构中的中间数据的系统和方法将中间数据存储在耦合在一个或多个流水线处理单元和外部存储器之间的共享高速缓存中。共享缓存提供多个流水线处理单元使用的存储。共享缓存的存储容量根据需要动态分配给不同的流水线处理单元，以避免停止上游单元，从而提高整体系统吞吐量。

16. 发明授权

US08700862B2 Compression status bit cache and backing store 有权
标题翻译：压缩状态位缓存和后备存储
公开(公告)号：US08700862B2
公开(公告)日：2014-04-15
申请号：US12327790
申请日：2008-12-03
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/00
CPC分类号： G06F12/0813 , G06F12/08 , G06F12/0875 , G06F12/128 , G06F2212/1024 , G06F2212/401
摘要： A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.
摘要翻译：压缩状态位缓存提供压缩状态位的片上可用性，用于确定需要多少位以访问潜在的压缩的存储器块。驻留在附加存储器的保留区域中的备份存储器为用于表示驻留在附加存储器中的任意大量块的压缩状态的一整套压缩状态位提供存储。用于在多个物理存储器设备上分配存储器访问模式的物理地址重映射（“swizzling”）被压缩状态位高速缓存部分地复制，以有效地整合后备存储数据与其他用户数据的分配和访问。

17. 发明授权

US08627041B2 Efficient line and page organization for compression status bit caching 有权
标题翻译：用于压缩状态位缓存的高效线和页组织
公开(公告)号：US08627041B2
公开(公告)日：2014-01-07
申请号：US12901452
申请日：2010-10-08
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts , Cass W. Everitt , Steven E. Molnar
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts , Cass W. Everitt , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/08 , G06F12/0875 , G06F12/1009 , G06F2212/401
摘要： One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.
摘要翻译：本发明的一个实施例提出了一种对包括任意数量的分区的虚拟映射的存储器系统中的压缩数据执行存储器访问请求的技术。虚拟地址被映射到由页表项（PTE）指定的线性物理地址。 PTE被配置为存储压缩属性，其用于定位压缩状态位缓存内的对应物理存储器页的压缩状态。压缩状态位缓存与压缩状态位后备存储一起操作。如果从压缩状态位缓存获得压缩状态，则存储器访问请求使用压缩状态进行。如果压缩状态位缓存未命中，则错误触发后备存储器的填充操作。填充完成后，使用新填充的压缩状态信息进行内存访问。

18. 发明授权

US08244984B1 System and method for cleaning dirty data in an intermediate cache using a data class dependent eviction policy 有权
标题翻译：使用依赖于数据类的驱逐策略来清理中间缓存中的脏数据的系统和方法
公开(公告)号：US08244984B1
公开(公告)日：2012-08-14
申请号：US12330467
申请日：2008-12-08
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John Edmondson
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , James Roberts , John Edmondson
IPC分类号： G06F13/00 , G06F12/12
CPC分类号： G06F12/0804 , G06F12/0897 , G06F12/126 , G06F2212/301 , G06F2212/302
摘要： In one embodiment, a method for managing information related to dirty data stored in an intermediate cache coupled to one or more clients and to an external memory includes receiving a dirty data notification related to dirty data residing in the intermediate cache, the dirty data notification including a memory address indicating a location in the external memory where the dirty data should be stored and a data type associated with the dirty data, and extracting a bank page number from the memory address that identifies a bank page within the external memory where the dirty data should be stored. The embodiment also includes incrementing a first count associated with a first entry in a notification sorter that is affirmatively associated with the bank page, determining that the dirty data has a first data type, and incrementing a second count associated with the first entry.
摘要翻译：在一个实施例中，用于管理与存储在耦合到一个或多个客户端和外部存储器的中间高速缓存中的脏数据有关的信息的方法包括接收与驻留在中间高速缓存中的脏数据相关的脏数据通知，该脏数据通知包括指示外部存储器中应该存储脏数据的位置的存储器地址和与脏数据相关联的数据类型，以及从识别外部存储器内的存储器页面的存储器地址提取存储体页号，其中脏数据应该存储。该实施例还包括增加与肯定与银行页面相关联的通知分类器中的与第一条目相关联的第一计数，确定脏数据具有第一数据类型，并递增与第一条目相关联的第二计数。

19. 发明授权

US08135926B1 Cache-based control of atomic operations in conjunction with an external ALU block 有权
公开(公告)号：US08135926B1
公开(公告)日：2012-03-13
申请号：US12255599
申请日：2008-10-21
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/02
CPC分类号： G06F12/084 , G06F9/3851 , G06F9/3881 , G06F12/0806
摘要： One embodiment of the invention sets forth a mechanism for efficiently processing atomic operations transmitted from multiple general processing clusters to an L2 cache. A tag look-up unit tracks the availability of each cache line in the L2 cache, reserves the necessary cache lines for the atomic operations and transmits the atomic operations to an ALU for processing. The tag look-up unit also increments a reference counter associated with a reserved cache line each time an atomic operation associated with that cache line is received. This feature allows multiple atomic operations associated with the same cache line to be pipelined to the ALU. A ROP unit that includes the ALU may request additional data necessary to process an atomic operation from the L2 cache. Result data is stored in the L2 cache and may also be returned to the general processing clusters.

20. 发明申请

US20100138614A1 Compression Status Bit Cache And Backing Store 有权
标题翻译：压缩状态位缓存和备份存储
公开(公告)号：US20100138614A1
公开(公告)日：2010-06-03
申请号：US12327790
申请日：2008-12-03
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/08 , G06F12/0875 , G06F12/128 , G06F2212/1024 , G06F2212/401
摘要： One embodiment of the present invention sets forth a technique for increasing available storage space within compressed blocks of memory attached to data processing chips, without requiring a proportional increase in on-chip compression status bits. A compression status bit cache provides on-chip availability of compression status bits used to determine how many bits are needed to access a potentially compressed block of memory. A backing store residing in a reserved region of attached memory provides storage for a complete set of compression status bits used to represent compression status of an arbitrarily large number of blocks residing in attached memory. Physical address remapping (“swizzling”) used to distribute memory access patterns over a plurality of physical memory devices is partially replicated by the compression status bit cache to efficiently integrate allocation and access of the backing store data with other user data.
摘要翻译：本发明的一个实施例提出了一种用于在附加到数据处理芯片的存储器的压缩块内增加可用存储空间的技术，而不需要片上压缩状态位的比例增加。压缩状态位缓存提供压缩状态位的片上可用性，用于确定需要多少位以访问潜在的压缩的存储器块。驻留在附加存储器的保留区域中的备份存储器为用于表示驻留在附加存储器中的任意大量块的压缩状态的一整套压缩状态位提供存储。用于在多个物理存储器设备上分配存储器访问模式的物理地址重映射（“swizzling”）被压缩状态位高速缓存部分地复制，以有效地整合后备存储数据与其他用户数据的分配和访问。

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