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11. 发明申请

US20130009315A1 INTERCONNECT STRUCTURES WITH ENGINEERED DIELECTRICS WITH NANOCOLUMNAR POROSITY 失效
标题翻译：具有纳米孔隙度的工程电介质的互连结构
公开(公告)号：US20130009315A1
公开(公告)日：2013-01-10
申请号：US11899842
申请日：2007-09-07
申请人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
发明人： Matthew E. Colburn , Satya V. Nitta , Sampath Purushothaman , Charles Black , Kathryn Guarini
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/7682 , H01L23/5222 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an interconnect structure with nanocolumnar intermetal dielectric is described involving the construction of an interconnect structure using a solid dielectric, and introducing a regular array of vertically aligned nanoscale pores through stencil formation and etching to form a hole array and subsequently pinching off the tops of the hole array with a cap dielectric. Variations of the method and means to construct a multilevel nanocolumnar interconnect structure are also described.
摘要翻译：描述了一种形成具有纳米柱状金属间电介质的互连结构的方法，涉及使用固体电介质构造互连结构，并通过模板形成和蚀刻引入垂直排列的纳米尺度孔的规则阵列以形成孔阵列并随后夹紧具有盖电介质的孔阵列的顶部。还描述了构建多层纳米柱状互连结构的方法和方法的变化。

12. 发明授权

US07045453B2 Very low effective dielectric constant interconnect structures and methods for fabricating the same 失效
标题翻译：非常低的有效介电常数互连结构及其制造方法
公开(公告)号：US07045453B2
公开(公告)日：2006-05-16
申请号：US11104764
申请日：2005-04-12
申请人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
发明人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
IPC分类号： H01L21/4763
CPC分类号： H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76885 , H01L2924/0002 , H01L2924/00
摘要： A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less-robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.
摘要翻译：一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能的互连。布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中布置非常低的k和较不稳定的间隙填充电介质，使得该结构将耐用层与强度非常相似低k电介质用于互连电气性能。

13. 发明授权

US07023093B2 Very low effective dielectric constant interconnect Structures and methods for fabricating the same 有权
标题翻译：非常低的有效介电常数互连结构及其制造方法
公开(公告)号：US07023093B2
公开(公告)日：2006-04-04
申请号：US10280283
申请日：2002-10-24
申请人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
发明人： Donald F. Canaperi , Timothy J. Dalton , Stephen M. Gates , Mahadevaiyer Krishnan , Satya V. Nitta , Sampath Purushothaman , Sean P. E. Smith
IPC分类号： H01L23/48
CPC分类号： H01L21/76807 , H01L21/76834 , H01L21/76835 , H01L21/76885 , H01L2924/0002 , H01L2924/00
摘要： A structure incorporates very low dielectric constant (k) insulators with copper wiring to achieve high performance interconnects. The wiring is supported by a relatively durable low k dielectric such as SiLk or SiO2 and a very low k and less robust gap fill dielectric is disposed in the remainder of the structure, so that the structure combines a durable layer for strength with a very low k dielectric for interconnect electrical performance.
摘要翻译：一个结构包含非常低的介电常数（k）绝缘体与铜布线，以实现高性能互连。布线由相对耐用的低k电介质（例如SiLk或SiO 2）支撑，并且在该结构的其余部分中设置非常低的k和较不牢固的间隙填充电介质，使得该结构将耐用层与强度非常低 k电介质用于互连电性能。

14. 发明申请

US20110020753A1 Method for reversing tone of patterns on integrated circuit and patterning sub-lithography trenches 审中-公开
标题翻译：用于在集成电路上反转图案色调和图案化亚光刻沟槽的方法
公开(公告)号：US20110020753A1
公开(公告)日：2011-01-27
申请号：US12510001
申请日：2009-07-27
申请人： Lawrence A. Clevenger , Maxime Darnon , Anthony D. Lisi , Satya V. Nitta
发明人： Lawrence A. Clevenger , Maxime Darnon , Anthony D. Lisi , Satya V. Nitta
IPC分类号： G03F7/20
CPC分类号： G03F7/091 , G03F7/40 , H01L21/3086
摘要： A method for reversing the tone of a lithographic image on a substrate comprises depositing a modifiable material on a substrate; applying a photolithographic material on the modifiable material: defining a removable patterned area in the photolithopgraphic material by photolithograpic means; removing the patterned area to produce an exposed region in the modifiable material that substantially conforms to the patterned area; producing a reacted modifiable material by increasing the etch resistance of the modifable material substantially throughout the exposed region so that the etch resistance of the exposed region comprises a region that substantially conforms to the exposed region; and removing the photoresist and the modifiable material to leave the reacted modifiable material and substrate.
摘要翻译：用于反转基底上的平版印刷图像的色调的方法包括将可修改材料沉积在基底上; 将光刻材料施加在可修改的材料上：通过光刻手段在光致剪切材料中限定可移除的图案区域; 去除所述图案化区域以在所述可修改材料中产生基本上符合所述图案化区域的暴露区域; 通过增加可修饰材料的基本上在整个曝光区域的耐蚀刻性而产生可反应的可修饰材料，使得暴露区域的耐蚀刻性包括基本上符合曝光区域的区域; 并除去光致抗蚀剂和可修改的材料以留下可反应的可修改的材料和基材。

15. 发明申请

US20090298281A1 INTERCONNECT STRUCTURE WITH HIGH LEAKAGE RESISTANCE 审中-公开
标题翻译：具有高耐漏电性的互连结构
公开(公告)号：US20090298281A1
公开(公告)日：2009-12-03
申请号：US12539488
申请日：2009-08-11
申请人： Chih-Chao Yang , Satya V. Nitta
发明人： Chih-Chao Yang , Satya V. Nitta
IPC分类号： H01L21/768
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76877 , H01L21/76883 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the dielectric material, the conductive material of the interconnect structure is surrounded on all sides (i.e., sidewall surfaces, upper surface and bottom surface) by a diffusion barrier material. Unlike prior art interconnect structures, the barrier material located on the upper surface of the recessed conductive material is located with an opening including the recessed conductive material.
摘要翻译：提供了互连结构，其中导电特征（即，导电材料）不与电介质材料的上表面共面，而是导电材料凹陷在电介质材料的上表面下方。除了凹陷在介电材料的上表面之外，互连结构的导电材料通过扩散阻挡材料在所有侧面（即，侧壁表面，上表面和底表面）上被包围。与现有技术的互连结构不同，位于凹陷导电材料的上表面上的阻挡材料定位成具有包括凹入的导电材料的开口。

16. 发明申请

US20090075470A1 Method for Manufacturing Interconnect Structures Incorporating Air-Gap Spacers 审中-公开
标题翻译：制造连接结构的空气间隙隔离器的方法
公开(公告)号：US20090075470A1
公开(公告)日：2009-03-19
申请号：US11855280
申请日：2007-09-14
申请人： Satya V. Nitta , Shom Ponoth
发明人： Satya V. Nitta , Shom Ponoth
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/7682 , H01L2221/1063
摘要： Methods for manufacturing air-gap (e.g., side wall air-gap) containing metal/insulator interconnect structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging comprise forming the air-gap spacers by deviating from a conventional dual-damascene etch process in order to avoid damage to the dielectric, and instead utilize intentional and controlled chemical damage of the Si, C, O, H containing dielectric by appropriate strip/ash etch chemistries after the trench etch and/or after via etch. The damaged dielectric layer is left in place after etch and the stack is taken through metallization and chemical mechanical planarization (CMP) processes. Subsequent to this, selective removal of the oxide-like damaged layer takes place by exposure to appropriate chemistries such as dilute HF, leaving behind air-gap spacers. Pinch-off cap deposition ensures integration of the air-gap for narrow air-gaps or perforated caps for wide air-gaps.
摘要翻译：用于制造用于超大规模集成（VLSI）和超大规模集成（ULSI）装置和包装的含有金属/绝缘体互连结构的气隙（例如，侧壁气隙）的方法包括通过偏离常规的双镶嵌蚀刻工艺，以避免损坏电介质，而是在沟槽蚀刻之后和/或之后通过适当的带/灰蚀刻化学处理使用含有Si，C，O，H的电介质的有意和受控的化学损伤通过蚀刻。蚀刻后损坏的介电层留在原位，堆叠通过金属化和化学机械平面化（CMP）工艺。此后，通过暴露于适当的化学物质（例如稀HF），留下气隙间隔物，可以选择性除去氧化物样损伤层。夹断盖沉积确保了用于宽气隙的窄气隙或穿孔盖的气隙的集成。

17. 发明申请

US20110210448A1 Interconnect Structures Incorporating Air-Gap Spacers 审中-公开
标题翻译：互连结构包含气隙隔离器
公开(公告)号：US20110210448A1
公开(公告)日：2011-09-01
申请号：US13083550
申请日：2011-04-09
申请人： Satya V. Nitta , Shom Ponoth
发明人： Satya V. Nitta , Shom Ponoth
IPC分类号： H01L23/48 , B82Y99/00
CPC分类号： H01L21/76807 , H01L21/31111 , H01L21/76802 , H01L21/76808 , H01L21/7682 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76877 , H01L23/48 , H01L23/481 , H01L23/52 , H01L23/522 , H01L23/5222 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.
摘要翻译：双镶嵌制品包括包含导电金属柱的沟槽，其中沟槽和导电金属柱向下延伸并且与通孔邻接。沟槽和导电金属柱和通孔具有共同的轴线。这些物品包括包含用于超大规模集成（VLSI）和超大规模集成（ULSI）设备和包装的金属/绝缘体结构的气隙间隔物的互连结构。在这方面的沟槽包括紧邻沟槽的侧壁和导电金属柱的侧壁气隙，侧壁气隙向下延伸到通孔，深度低于由沟槽的底部固定的线，以及在通孔中向下延伸距离线下方约1埃至通孔的整个深度。在另一方面，制品包括封盖的双镶嵌结构。

18. 发明申请

US20110121457A1 Process for Reversing Tone of Patterns on Integrated Circuit and Structural Process for Nanoscale Production 有权
标题翻译：集成电路模式和纳米级生产结构过程逆转过程
公开(公告)号：US20110121457A1
公开(公告)日：2011-05-26
申请号：US13021774
申请日：2011-02-06
申请人： Lawrence A. Clevenger , Maxime Darnon , Anthony D. Lisi , Satya V. Nitta
发明人： Lawrence A. Clevenger , Maxime Darnon , Anthony D. Lisi , Satya V. Nitta
IPC分类号： H01L23/532 , H01L21/311
CPC分类号： H01L21/31144 , H01L21/7682
摘要： A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.
摘要翻译：在具有电介质层的基板上产生气隙的方法包括通过需要气隙的光刻来定义线。线的尺寸通过修整工艺（各向同性蚀刻）收缩。图案的色调通过施加被向下蚀刻到图案的顶部的平坦化层来反转。去除光致抗蚀剂，导致亚光刻沟槽，其转移到盖层中，最终转移到两条金属线之间的电介质中。暴露的电介质最终被损坏，并被蚀刻掉，导致金属线之间的气隙。间隙通过在随后的电介质的沉积期间发生的夹断来密封。

19. 发明授权

US07939446B1 Process for reversing tone of patterns on integerated circuit and structural process for nanoscale fabrication 有权
标题翻译：整流电路图案的反转色调和纳米尺寸制作的结构工艺
公开(公告)号：US07939446B1
公开(公告)日：2011-05-10
申请号：US12616259
申请日：2009-11-11
申请人： Lawrence A. Clevenger , Maxime Darnon , Anthony D. Lisi , Satya V. Nitta
发明人： Lawrence A. Clevenger , Maxime Darnon , Anthony D. Lisi , Satya V. Nitta
IPC分类号： H01L21/00
CPC分类号： H01L21/31144 , H01L21/7682
摘要： A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.
摘要翻译：在具有电介质层的基板上产生气隙的方法包括通过需要气隙的光刻来定义线。线的尺寸通过修整工艺（各向同性蚀刻）收缩。图案的色调通过施加被向下蚀刻到图案的顶部的平坦化层来反转。去除光致抗蚀剂，导致亚光刻沟槽，其转移到盖层中，最终转移到两条金属线之间的电介质中。暴露的电介质最终被损坏，并被蚀刻掉，导致金属线之间的气隙。间隙通过在随后的电介质的沉积期间发生的夹断来密封。

20. 发明授权

US09305882B2 Interconnect structures incorporating air-gap spacers 有权
标题翻译：包含气隙间隔件的互连结构
公开(公告)号：US09305882B2
公开(公告)日：2016-04-05
申请号：US13083550
申请日：2011-04-09
申请人： Satya V. Nitta , Shom Ponoth
发明人： Satya V. Nitta , Shom Ponoth
IPC分类号： H01L23/52 , H01L23/532 , H01L23/48 , H01L23/522 , H01L21/768
CPC分类号： H01L21/76807 , H01L21/31111 , H01L21/76802 , H01L21/76808 , H01L21/7682 , H01L21/76826 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L21/76834 , H01L21/76877 , H01L23/48 , H01L23/481 , H01L23/52 , H01L23/522 , H01L23/5222 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2221/1063 , H01L2924/0002 , H01L2924/00
摘要： A dual damascene article of manufacture comprises a trench containing a conductive metal column where the trench and the conductive metal column extend down into and are contiguous with a via. The trench and the conductive metal column and the via have a common axis. These articles comprise interconnect structures incorporating air-gap spacers containing metal/insulator structures for Very Large Scale Integrated (VLSI) and Ultra Large Scale Integrated (ULSI) devices and packaging. The trench in this regard comprises a sidewall air-gap immediately adjacent the side walls of the trench and the conductive metal column, the sidewall air-gap extending down to the via to a depth below a line fixed by the bottom of the trench, and continues downward in the via for a distance of from about 1 Angstrom below the line to the full depth of the via. In another aspect, the article of manufacture comprises a capped dual damascene structure.
摘要翻译：双镶嵌制品包括包含导电金属柱的沟槽，其中沟槽和导电金属柱向下延伸并且与通孔邻接。沟槽和导电金属柱和通孔具有共同的轴线。这些物品包括包含用于超大规模集成（VLSI）和超大规模集成（ULSI）设备和包装的金属/绝缘体结构的气隙间隔物的互连结构。在这方面的沟槽包括紧邻沟槽的侧壁和导电金属柱的侧壁气隙，侧壁气隙向下延伸到通孔，深度低于由沟槽的底部固定的线，以及在通孔中向下延伸距离线下方约1埃至通孔的整个深度。在另一方面，制品包括封盖的双镶嵌结构。

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