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11. 发明授权

US07309638B2 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US07309638B2
公开(公告)日：2007-12-18
申请号：US11182597
申请日：2005-07-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

12. 发明授权

US07276419B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US07276419B2
公开(公告)日：2007-10-02
申请号：US11264068
申请日：2005-10-31
申请人： Vishnu Khemka , John M. Pigott , Ronghua Zhu , Amitava Bose , Randall C. Gray , Jeffrey J. Braun
发明人： Vishnu Khemka , John M. Pigott , Ronghua Zhu , Amitava Bose , Randall C. Gray , Jeffrey J. Braun
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dopant type. A second region between the first region and the second semiconductor layer may have the first dopant type. A third region above the second region may have the first dopant type. A fourth semiconductor region adjacent to the third region may have a first concentration of the second dopant type. A source contact region may have a second concentration of the second dopant type adjacent to the third semiconductor region and adjacent to the fourth semiconductor region. The second concentration may be higher than the first concentration.
摘要翻译：半导体器件可以包括第一，第二和第三半导体层。第一和第三层可以具有第一掺杂剂类型，并且第二层可以具有第二掺杂剂类型。第三半导体层内的第一区域可以具有第二掺杂剂类型。第一区域和第二半导体层之间的第二区域可以具有第一掺杂剂类型。第二区域上方的第三区域可以具有第一掺杂剂类型。与第三区域相邻的第四半导体区域可以具有第二掺杂剂类型的第一浓度。源极接触区域可以具有与第三半导体区域相邻并且与第四半导体区域相邻的第二掺杂剂类型的第二浓度。第二浓度可能高于第一浓度。

13. 发明申请

US20070200184A1 Methods and apparatus for a stepped-drift MOSFET 有权
标题翻译：梯形漂移MOSFET的方法和装置
公开(公告)号：US20070200184A1
公开(公告)日：2007-08-30
申请号：US11361624
申请日：2006-02-24
申请人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Todd Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Todd Roggenbauer
IPC分类号： H01L29/76 , H01L21/332
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A power metal-oxide-semiconductor field effect transistor (MOSFET) (100) incorporates a stepped drift region including a shallow trench insulator (STI) (112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.
摘要翻译：功率金属氧化物半导体场效应晶体管（MOSFET）（100）包括阶梯状漂移区域，其包括与栅极（114）部分重叠的浅沟槽绝缘体（112），并将距离的一部分延伸到漏区（122）。硅化物块从STI（112）和漏极区（122）延伸并部分重叠。 STI（112）的宽度为漂移区域的大约50％至75％。

14. 发明申请

US20060273402A1 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060273402A1
公开(公告)日：2006-12-07
申请号：US11144569
申请日：2005-06-02
申请人： Vishnu Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7393 , H01L29/0634 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200, 300, 400) that includes a semiconductor substrate (110, 210, 310, 410) having a first conductivity type and buried semiconductor region (115, 215, 315, 415) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120, 220, 320, 420) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130, 230, 330, 430) having the first conductivity type located above the first semiconductor region, a third semiconductor region (140, 240, 340, 440) having the second conductivity type located above the first semiconductor region, an emitter (150, 250, 350, 450) having the first conductivity type disposed in the third semiconductor region, and a collector (170, 270, 370, 470) having the first conductivity type disposed in the third semiconductor region. In a particular embodiment, the third semiconductor region and the buried semiconductor region deplete the first semiconductor region in response to a reverse bias applied between the second semiconductor region and the third semiconductor region.
摘要翻译：一种包括绝缘栅双极晶体管（IGBT）（100,200,300,400）的半导体元件和制造方法，包括具有第一导电类型和掩埋半导体区域的半导体衬底（110,210,310,410） 115,215,315,415），其具有位于半导体衬底上方的第二导电类型。 IGBT还包括具有位于掩埋半导体区域上方的第一导电类型的第一半导体区域（120,220,320,420），具有第一导电类型的第二半导体区域（130,230,330,430）位于第二半导体区域第一半导体区域，具有位于第一半导体区域上方的第二导电类型的第三半导体区域（140,240,340,440），具有设置在第三半导体区域中的第一导电类型的发射极（150,250,350,450）以及设置在第三半导体区域中的具有第一导电类型的集电极（170,270,370,470）。在特定实施例中，第三半导体区域和掩埋半导体区域响应于施加在第二半导体区域和第三半导体区域之间的反向偏压而耗尽第一半导体区域。

15. 发明申请

US20060244081A1 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体器件及其形成方法
公开(公告)号：US20060244081A1
公开(公告)日：2006-11-02
申请号：US11426815
申请日：2006-06-27
申请人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Vijay Parthasarathy
发明人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Vijay Parthasarathy
IPC分类号： H01L29/76
CPC分类号： H01L29/7391 , H01L29/861
摘要： In one embodiment, semiconductor device 10 comprises a diode which uses isolation regions (34, 16, and 13) and a plurality of dopant concentrations (30, 20, 24, and 26) which may be used to limit the parasitic current that is injected into the semiconductor substrate (12). Various biases on the isolation regions (34, 16, and 13) may be used to affect the behavior of semiconductor device (10). In addition, a conductive layer (28) may be formed overlying the junction between anode (42) and cathode (40). This conductive layer (28) may decrease the electric field in selected regions in order to increase the maximum voltage that may be applied to cathode (40).
摘要翻译：在一个实施例中，半导体器件10包括使用隔离区域（34,16和13）和多个掺杂剂浓度（30,20,24和26）的二极管，其可用于限制注入的寄生电流进入半导体基板（12）。可以使用隔离区域（34,16和13）上的各种偏压来影响半导体器件（10）的行为。此外，可以形成覆盖在阳极（42）和阴极（40）之间的连接处的导电层（28）。为了增加施加到阴极（40）的最大电压，该导电层（28）可以减小选定区域中的电场。

16. 发明申请

US20060014342A1 Method of manufacturing a semiconductor component 有权
标题翻译：制造半导体部件的方法
公开(公告)号：US20060014342A1
公开(公告)日：2006-01-19
申请号：US11182597
申请日：2005-07-14
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd Roggenbauer
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose , Todd Roggenbauer
IPC分类号： H01L21/8234 , H01L21/8222 , H01L21/20
CPC分类号： H01L29/866 , H01L27/0255 , H01L27/0814 , Y10S438/983
摘要： A semiconductor component comprises a first semiconductor region (110, 310), a second semiconductor region (120, 320) above the first semiconductor region, a third semiconductor region (130, 330) above the second semiconductor region, a fourth semiconductor region (140, 340) above the third semiconductor region, a fifth semiconductor region (150, 350) above the second semiconductor region and at least partially contiguous with the fourth semiconductor region, a sixth semiconductor region (160, 360) above and electrically shorted to the fifth semiconductor region, and an electrically insulating layer (180, 380) above the fourth semiconductor region and the fifth semiconductor region. A junction (145, 345) between the fourth semiconductor region and the fifth semiconductor region forms a zener diode junction, which is located only underneath the electrically insulating layer. In one embodiment, a seventh semiconductor region (170) circumscribes the third, fourth, fifth, and sixth semiconductor regions.
摘要翻译：半导体部件包括第一半导体区域（110,310），第一半导体区域上方的第二半导体区域（120,320），第二半导体区域上方的第三半导体区域（130,330），第四半导体区域（140,320），340），在所述第二半导体区域上方并且与所述第四半导体区域至少部分邻接的第五半导体区域（150,350），在所述第三半导体区域上方的第六半导体区域（160,360），并且电气短路到所述第五半导体区域半导体区域，以及位于第四半导体区域和第五半导体区域上方的电绝缘层（180,380）。在第四半导体区域和第五半导体区域之间的结（145,345）形成仅位于电绝缘层下方的齐纳二极管结。在一个实施例中，第七半导体区域（170）围绕第三，第四，第五和第六半导体区域。

17. 发明申请

US20060001057A1 Schottky device and method of forming 有权
标题翻译：肖特基器件和成型方法
公开(公告)号：US20060001057A1
公开(公告)日：2006-01-05
申请号：US10881678
申请日：2004-06-30
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/80 , H01L21/338
CPC分类号： H01L29/66143 , H01L29/812 , H01L29/872
摘要： A conductive layer includes a first portion that forms a Schottky region with an underlying first region having a first conductivity type. A second region of a second conductivity type underlies the first region, where the second conductivity type is opposite the first conductivity type. A third region of the first conductivity type immediately underlies the second region and is electrically coupled to a cathode of the device.
摘要翻译：导电层包括形成具有第一导电类型的下面的第一区域的肖特基区域的第一部分。第二导电类型的第二区域位于第一区域的正下方，其中第二导电类型与第一导电类型相反。第一导电类型的第三区域刚好在第二区域的下面，并且电耦合到器件的阴极。

18. 发明申请

US20080293211A1 High voltage deep trench capacitor 失效
标题翻译：高压深沟槽电容器
公开(公告)号：US20080293211A1
公开(公告)日：2008-11-27
申请号：US11752608
申请日：2007-05-23
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/20
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

19. 发明申请

US20050285188A1 LDMOS transistor 有权
标题翻译： LDMOS晶体管
公开(公告)号：US20050285188A1
公开(公告)日：2005-12-29
申请号：US10875105
申请日：2004-06-23
申请人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
发明人： Vishnu Khemka , Vijay Parthasarathy , Ronghua Zhu , Amitava Bose
IPC分类号： H01L29/06 , H01L29/47 , H01L29/76 , H01L29/78
CPC分类号： H01L29/782 , H01L27/0727 , H01L29/0619 , H01L29/0653 , H01L29/47 , H01L29/66659 , H01L29/66681 , H01L29/7835
摘要： An LDMOS transistor has a Schottky diode inserted at the center of a doped region of the LDMOS transistor. A Typical LDMOS transistor has a drift region in the center. In this case a Schottky diode is inserted at the center of this drift region which has the effect of providing a Schottky diode connected from source to drain in the forward direction so that the drain voltage is clamped to a voltage that is lower than the PN junction threshold, thereby avoiding forward biasing the PN junction. An alternative is to insert the Schottky diode at the well in which the source is formed, which is on the periphery of the LDMOS transistor. In such case the Schottky diode is formed differently but still is connected from source to drain in the forward direction to achieve the desired voltage clamping at the drain.
摘要翻译： LDMOS晶体管具有插入在LDMOS晶体管的掺杂区域的中心处的肖特基二极管。典型的LDMOS晶体管在中心具有漂移区域。在这种情况下，肖特基二极管插在该漂移区的中心，其具有提供从正向连接到源极到漏极的肖特基二极管的作用，使得漏极电压被钳位到低于PN结的电压阈值，从而避免正向偏置PN结。一种替代方案是将肖特基二极管插入其中形成源的阱，其位于LDMOS晶体管的外围。在这种情况下，肖特基二极管的形成方式不同，但仍然在正向方向上从源极到漏极连接，以在漏极处实现所需的电压钳位。

20. 发明申请

US20050275055A1 Schottky device 失效
标题翻译：肖特基装置
公开(公告)号：US20050275055A1
公开(公告)日：2005-12-15
申请号：US10856602
申请日：2004-05-28
申请人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose
发明人： Vijay Parthasarathy , Vishnu Khemka , Ronghua Zhu , Amitava Bose
IPC分类号： H01L27/06 , H01L27/07 , H03K19/00
CPC分类号： H01L27/0727 , H01L27/0629
摘要： A regular Schottky diode or a device that has a Schottky diode characteristic and an MOS transistor are coupled in series to provide a significant improvement in leakage current and breakdown voltage with only a small degradation in forward current. In the reverse bias case, there is a small reverse bias current but the voltage across the Schottky diode remains small due the MOS transistor. Nearly all of the reverse bias voltage is across the MOS transistor until the MOS transistor breaks down. This transistor breakdown, however, is not initially destructive because the Schottky diode limits the current. As the reverse bias voltage continues to increase the Schottky diodes begins to absorb more of the voltage. This increases the leakage current but the breakdown voltage is a somewhat additive between the transistor and the Schottky diode.
摘要翻译：正交肖特基二极管或具有肖特基二极管特性和MOS晶体管的器件串联耦合以提供泄漏电流和击穿电压的显着改进，只有正向电流的降低很小。在反向偏置情况下，存在小的反向偏置电流，但由于MOS晶体管，肖特基二极管两端的电压保持较小。几乎所有的反向偏置电压都跨越MOS晶体管，直到MOS晶体管故障。然而，该晶体管击穿不是最初的破坏性，因为肖特基二极管限制了电流。随着反向偏压持续增加，肖特基二极管开始吸收更多的电压。这增加了漏电流，但是在晶体管和肖特基二极管之间的击穿电压稍微相加。

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