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11. 发明授权

US08675298B2 Systems and methods for adaptive target search 有权
标题翻译：自适应目标搜索的系统和方法
公开(公告)号：US08675298B2
公开(公告)日：2014-03-18
申请号：US12992933
申请日：2009-01-09
申请人： Jingfeng Liu , Hongwei Song
发明人： Jingfeng Liu , Hongwei Song
IPC分类号： G11B5/035 , G11B20/10
CPC分类号： G11B20/10009 , G11B5/035 , G11B5/09 , G11B20/10046 , G11B20/10212 , G11B20/10481 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include both a main data processing circuit and an adaptive setting determination circuit. The main data processing circuit receives a series of data samples and includes: an equalizer circuit and a data detector circuit. The equalizer circuit receives the series of data samples and provides an equalized output. The equalizer circuit is controlled at least in part by a coefficient. The data detector circuit receives the equalizer output and provides a main data output based at least in part on a target. The adaptive setting determination circuit receives the series of data samples and the main data output, and operates in parallel with the main data processing circuit to adaptively determine the coefficient and the target.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，本发明的一些实施例提供了包括主数据处理电路和自适应设置确定电路的数据处理电路。主数据处理电路接收一系列数据样本，包括：均衡器电路和数据检测器电路。均衡器电路接收一系列数据样本并提供均衡的输出。均衡器电路至少部分地由系数控制。数据检测器电路接收均衡器输出并且至少部分地基于目标提供主数据输出。自适应设置确定电路接收一系列数据样本和主数据输出，并与主数据处理电路并行操作，以自适应地确定系数和目标。

12. 发明授权

US08422609B2 Automatic filter-reset mechanism 失效
标题翻译：自动过滤器复位机构
公开(公告)号：US08422609B2
公开(公告)日：2013-04-16
申请号：US12570326
申请日：2009-09-30
申请人： Jingfeng Liu , Haotian Zhang , Hongwei Song , Lingyan Sun
发明人： Jingfeng Liu , Haotian Zhang , Hongwei Song , Lingyan Sun
IPC分类号： H04B1/10
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10481 , H03H17/0294
摘要： In one embodiment, a (hard-drive) read channel has a (DFIR equalization) filter, whose tap coefficients are adaptively updated. A reset controller monitors an (LLR) signal generated downstream of the filter to automatically determine when to reset the filter, e.g., by reloading an initial set of user-specified tap coefficients. For LLR values, the reset controller determines to reset the filter when the reset controller detects that too many recent LLR values have confidence values that are too low. When implemented in a hard-drive read channel, the reset controller can reset the filter one or more times during read operations within a sector of the hard drive.
摘要翻译：在一个实施例中，（硬盘驱动器）读通道具有（DFIR均衡）滤波器，其抽头系数被自适应地更新。复位控制器监视在滤波器下游产生的（LLR）信号，以自动确定何时复位滤波器，例如通过重新加载用户指定的抽头系数的初始集合。对于LLR值，当复位控制器检测到过多的近期LLR值具有太低的置信度值时，复位控制器确定复位滤波器。当在硬盘驱动器读取通道中实现时，复位控制器可以在硬盘驱动器的扇区内的读取操作期间复位一次或多次过滤器。

13. 发明授权

US08208213B2 Systems and methods for hybrid algorithm gain adaptation 有权
标题翻译：混合算法增益适应的系统和方法
公开(公告)号：US08208213B2
公开(公告)日：2012-06-26
申请号：US12792555
申请日：2010-06-02
申请人： Jingfeng Liu , Hongwei Song
发明人： Jingfeng Liu , Hongwei Song
IPC分类号： G11B20/10
CPC分类号： G11B20/10009 , G11B20/10027 , G11B20/10462 , G11B2020/1287 , G11B2220/2516 , H03G1/0088
摘要： Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier, a gain circuit, and hybrid gain feedback combination circuit. The variable gain amplifier is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The gain circuit is operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output. The hybrid gain feedback combination circuit is operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern.
摘要翻译：本发明的各种实施例提供了用于数据处理的系统和方法。例如，本发明的一些实施例提供包括可变增益放大器，增益电路和混合增益反馈组合电路的数据处理电路。可变增益放大器可操作以将增益应用于对应于增益反馈值的数据输入并提供放大的输出。增益电路可操作以至少部分地基于放大的输出来计算第一算法误差分量和第二算法误差分量。当数据输入包括同步模式时，混合增益反馈组合电路可操作地组合第一算法误差分量和第二算法误差分量以产生增益反馈值。

14. 发明授权

US07948699B2 Systems and methods for equalizer optimization in a storage access retry 有权
标题翻译：存储访问重试中均衡器优化的系统和方法
公开(公告)号：US07948699B2
公开(公告)日：2011-05-24
申请号：US12348236
申请日：2009-01-02
申请人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
发明人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10481 , G11B20/18 , G11B2020/183 , G11B2220/2516
摘要： Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
摘要翻译：本发明的各种实施例提供了包括多路复用器，存储器缓冲器，数据处理电路和通道设置修改电路的数据处理电路。多路复用器的第一输入接收输入数据集，多路复用器的第二输入接收缓冲数据集。复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。存储器缓冲器接收多路复用器输出并提供缓冲数据集。数据处理电路的操作至少部分由通道设置决定。数据处理电路接收复用器输出并执行数据检测处理。当数据检测过程失败时，选择信号被置位以选择缓冲数据集，当数据检测过程成功时，选择信号选择输入数据集。当数据检测处理失败时，通道设置修改电路可操作以修改通道设置。

15. 发明申请

US20110103527A1 Phase Detector For Timing Recovery Loop 有权
标题翻译：定时恢复回路相位检测器
公开(公告)号：US20110103527A1
公开(公告)日：2011-05-05
申请号：US12609031
申请日：2009-10-30
申请人： Jingfeng Liu , Hongwei Song
发明人： Jingfeng Liu , Hongwei Song
IPC分类号： H04L27/06 , H04L7/00
CPC分类号： G11B20/10009 , G11B20/10037 , G11B20/10055 , G11B20/10222 , G11B20/10296 , G11B2220/2516 , H03L7/07 , H03L7/0807 , H03L7/0812 , H03L7/091 , H03M1/1255 , H04L7/0054
摘要： In one embodiment, a (hard-drive) read channel has a phase detector used in a timing recovery loop. The phase detector utilizes the sign bit and confidence value from a received log-likelihood ratio (LLR) signal to generate a mean value. The mean value is convolved with a partial response target to generate an estimated timing error signal. When implemented in a hard-drive read channel, the phase detector allows for timing recovery with lower loss-of-lock rates.
摘要翻译：在一个实施例中，（硬盘驱动器）读通道具有在定时恢复循环中使用的相位检测器。相位检测器利用来自接收到的对数似然比（LLR）信号的符号位和置信度值来产生平均值。平均值与部分响应目标进行卷积以产生估计的定时误差信号。当在硬盘驱动器读取通道中实现时，相位检测器允许以较低的锁定失效率进行定时恢复。

16. 发明申请

US20100177419A1 AGC Loop with Weighted Zero Forcing and LMS Error Sources and Methods for Using Such 有权
标题翻译：具有加权零强制和LMS误差源的AGC环路及其使用方法
公开(公告)号：US20100177419A1
公开(公告)日：2010-07-15
申请号：US12352540
申请日：2009-01-12
申请人： Jingfeng Liu , Hongwei Song , Jongseung Park , George Mathew , Yuan Xing Lee
发明人： Jingfeng Liu , Hongwei Song , Jongseung Park , George Mathew , Yuan Xing Lee
IPC分类号： G11B5/00 , H03G3/30
CPC分类号： G11B5/09 , G11B20/10009 , G11B20/10027 , G11B20/10046 , H03G3/30 , H03M1/185
摘要： Various embodiments of the present invention provide systems and methods for gain control. For example, some embodiments of the present invention provide variable gain control circuits. Such circuits include a zero forcing loop generating a zero forcing feedback and a least mean square loop generating a least mean square feedback. An error quantization circuit generates a hybrid feedback based upon a threshold condition using the zero forcing feedback and the least mean square feedback. A variable gain amplifier is at least in part controlled by a derivative of the hybrid feedback.
摘要翻译：本发明的各种实施例提供用于增益控制的系统和方法。例如，本发明的一些实施例提供可变增益控制电路。这种电路包括产生零强制反馈的零强制环路和产生最小均方反馈的最小均方环路。误差量化电路使用零强制反馈和最小均方反馈基于阈值条件产生混合反馈。可变增益放大器至少部分地由混合反馈的导数来控制。

17. 发明申请

US20100172046A1 Systems and Methods for Equalizer Optimization in a Storage Access Retry 有权
标题翻译：存储访问重试中均衡器优化的系统和方法
公开(公告)号：US20100172046A1
公开(公告)日：2010-07-08
申请号：US12348236
申请日：2009-01-02
申请人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
发明人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： G11B20/10
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10481 , G11B20/18 , G11B2020/183 , G11B2220/2516
摘要： Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
摘要翻译：本发明的各种实施例提供了包括多路复用器，存储器缓冲器，数据处理电路和通道设置修改电路的数据处理电路。多路复用器的第一输入接收输入数据集，多路复用器的第二输入接收缓冲数据集。复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。存储器缓冲器接收多路复用器输出并提供缓冲数据集。数据处理电路的操作至少部分由通道设置决定。数据处理电路接收复用器输出并执行数据检测处理。当数据检测过程失败时，选择信号被置位以选择缓冲数据集，当数据检测过程成功时，选择信号选择输入数据集。当数据检测处理失败时，通道设置修改电路可操作以修改通道设置。

18. 发明授权

US07058873B2 Encoding method using a low density parity check code with a column weight of two 有权
标题翻译：编码方法使用一个列权重为2的低密度奇偶校验码
公开(公告)号：US07058873B2
公开(公告)日：2006-06-06
申请号：US10289780
申请日：2002-11-07
申请人： Hongwei Song , Vijayakumar Bhagavatula , Jingfeng Liu
发明人： Hongwei Song , Vijayakumar Bhagavatula , Jingfeng Liu
IPC分类号： H03M13/11 , H03M13/29 , H03M13/45
CPC分类号： H03M13/1111 , H03M13/116 , H03M13/1515 , H03M13/2906 , H04L1/0041 , H04L1/005 , H04L1/0057 , H04L1/0065
摘要： A method for communicating binary data and a digital communication system are presented. According to one embodiment, the method includes encoding a message word by multiplying the message word with a generator matrix, wherein the generator matrix multiplied by the transpose of a parity check matrix for a low density parity check code yields a null set, and wherein the parity check matrix has a column weight of two. Additionally disclosed is an encoding scheme based on a three-tier Tanner graph having a girth of twelve.
摘要翻译：提出了一种用于传送二进制数据和数字通信系统的方法。根据一个实施例，该方法包括通过将消息字与生成器矩阵相乘来对消息字进行编码，其中生成器矩阵乘以用于低密度奇偶校验码的奇偶校验矩阵的转置产生空集合，并且其中，奇偶校验矩阵的列权重为2。另外公开的是一种基于三层Tanner图的编码方案，其长度为十二分。

19. 发明授权

US09219469B2 Systems and methods for filter constraint estimation 有权
标题翻译：滤波器约束估计的系统和方法
公开(公告)号：US09219469B2
公开(公告)日：2015-12-22
申请号：US12887330
申请日：2010-09-21
申请人： Haotian Zhang , Hongwei Song , Jingfeng Liu , Yu Liao
发明人： Haotian Zhang , Hongwei Song , Jingfeng Liu , Yu Liao
IPC分类号： H03H7/30 , H04N11/02 , H03H17/02
CPC分类号： H03H17/0289 , H03H17/0294
摘要： Various embodiments of the present invention provide systems and methods for calibrating a data processing circuit. For example, a method for calibrating a data processing circuit is discussed that includes providing a digital filter, providing a detector circuit, and providing an analog filter. Operation of the digital filter is at least in part governed by filter taps that correspond to a filter tap constraint value. Operation of the detector circuit is at least in part governed by a target parameter. Operation of the analog filter is at least in part governed by an analog parameter that is one of a plurality of analog parameters. The methods further include selecting a target parameter, and calculating the filter tap constraint value based on the target parameter. Combinations of the target parameter, the calculated filter tap constraint value, and each of the plurality of analog parameters are applied to identify the analog parameter.
摘要翻译：本发明的各种实施例提供了用于校准数据处理电路的系统和方法。例如，讨论了一种用于校准数据处理电路的方法，其包括提供数字滤波器，提供检测器电路和提供模拟滤波器。数字滤波器的操作至少部分地由对应于滤波器抽头约束值的滤波器抽头来控制。检测器电路的操作至少部分地由目标参数控制。模拟滤波器的操作至少部分地由作为多个模拟参数之一的模拟参数来控制。所述方法还包括选择目标参数，以及基于所述目标参数来计算所述滤波器抽头约束值。应用目标参数，计算滤波器抽头约束值和多个模拟参数中的每一个的组合以识别模拟参数。

20. 发明授权

US08996597B2 Nyquist constrained digital finite impulse response filter 有权
标题翻译：奈奎斯特约束数字有限脉冲响应滤波器
公开(公告)号：US08996597B2
公开(公告)日：2015-03-31
申请号：US13272209
申请日：2011-10-12
申请人： Yu Liao , Hongwei Song , Jingfeng Liu , Haotian Zhang
发明人： Yu Liao , Hongwei Song , Jingfeng Liu , Haotian Zhang
IPC分类号： G06F17/10 , G06F17/15 , H03H17/06 , H03H17/02
CPC分类号： G06F17/15 , H03H17/06 , H03H2017/0222
摘要： Various embodiments of the present invention provide apparatuses and methods for filtering a digital signal with a Nyquist constrained digital finite impulse response filter. For example, an apparatus for filtering digital data is disclosed that includes a digital finite impulse response filter having a plurality of taps. The apparatus also includes a tap weight controller connected to the digital finite impulse response filter, operable to adjust a tap weight for each of a subset of the taps such that a magnitude of a Nyquist response of the digital finite impulse response filter remains within a constraint range.
摘要翻译：本发明的各种实施例提供了用奈奎斯特约束数字有限脉冲响应滤波器对数字信号进行滤波的装置和方法。例如，公开了一种用于对数字数据进行滤波的装置，其包括具有多个抽头的数字有限脉冲响应滤波器。该装置还包括连接到数字有限脉冲响应滤波器的抽头加权控制器，可操作以调整抽头子集中的每一个的抽头权重，使得数字有限脉冲响应滤波器的奈奎斯特响应的幅度保持在约束范围。

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