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11. 发明授权

US08455858B2 Semiconductor structure for reducing band-to-band tunneling (BTBT) leakage 有权
标题翻译：半导体结构用于减少带内隧穿（BTBT）泄漏
公开(公告)号：US08455858B2
公开(公告)日：2013-06-04
申请号：US13120122
申请日：2010-11-08
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/7391 , H01L29/1054 , H01L29/165 , H01L29/7833 , H01L29/785
摘要： A semiconductor structure is provided. The semiconductor structure may include a substrate (100); a buffer layer or an insulation layer (200) formed on the substrate; a first strained wide bandgap semiconductor material layer (400) formed on the buffer layer or the insulation layer; a strained narrow bandgap semiconductor material layer (500) formed on the first strained wide bandgap semiconductor material layer; a second strained wide bandgap semiconductor material layer (700) formed on the strained narrow bandgap semiconductor material layer; a gate stack (300) formed on the second strained wide bandgap semiconductor material layer; and a source and a drain (600) formed in the first strained wide bandgap semiconductor material layer, the strained narrow bandgap semiconductor material layer and the second strained wide bandgap semiconductor material layer respectively.
摘要翻译：提供半导体结构。半导体结构可以包括衬底（100）; 形成在所述基板上的缓冲层或绝缘层（200）; 形成在缓冲层或绝缘层上的第一应变宽带隙半导体材料层（400）形成在第一应变宽带隙半导体材料层上的应变窄带隙半导体材料层（500）形成在应变窄带隙半导体材料层上的第二应变宽带隙半导体材料层（700）形成在第二应变宽带隙半导体材料层上的栅叠层（300）以及形成在第一应变宽带隙半导体材料层中的源极和漏极（600），应变窄带隙半导体材料层和第二应变宽带隙半导体材料层。

12. 发明申请

US20120228707A1 STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：应变导电绝缘体结构及其形成方法
公开(公告)号：US20120228707A1
公开(公告)日：2012-09-13
申请号：US13263222
申请日：2011-08-25
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/78684 , H01L29/7846
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a plurality of shallow trench isolation structures extending into the silicon substrate and filled with an insulating dielectric material to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：硅衬底，其中在硅衬底的表面上形成氧化物绝缘层; 形成在所述氧化物绝缘层上的Ge层，其中在所述Ge层和所述氧化物绝缘层之间形成第一钝化层; 形成在Ge层上的栅极叠层，形成在栅叠层下方的沟道区，以及形成在沟道区的侧面上的源极和漏极; 以及延伸到硅衬底中并填充有绝缘电介质材料以在沟道区域中产生应变的多个浅沟槽隔离结构。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

13. 发明申请

US20120187487A1 GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：导通绝缘体结构及其形成方法
公开(公告)号：US20120187487A1
公开(公告)日：2012-07-26
申请号：US13201903
申请日：2011-07-07
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L29/78684 , H01L21/28255 , H01L21/76256 , H01L29/66742 , H01L29/78603
摘要： A method for forming a Ge-on-insulator structure is provided, comprising steps of: forming a Ge layer (1200) on a substrate (2000); treating a first surface of the Ge layer (1200) to form a first semiconducting metal-germanide passivation layer (1300); bonding the first semiconducting metal-germanide passivation layer (1300) with a silicon substrate (1100), wherein on a surface of the silicon substrate (1100) an oxide insulating layer is formed; and removing the substrate (2000). Further, a Ge-on-insulator structure formed by the method is also provided.
摘要翻译：提供一种形成绝缘体上Ge结构的方法，包括以下步骤：在衬底（2000）上形成Ge层（1200）; 处理所述Ge层（1200）的第一表面以形成第一半导体金属 - 锗化物钝化层（1300）; 将第一半导体金属 - 锗化物钝化层（1300）与硅衬底（1100）接合，其中在所述硅衬底（1100）的表面上形成氧化物绝缘层; 并移除基板（2000）。此外，还提供了通过该方法形成的绝缘体上Ge结构。

14. 发明申请

US20140145314A1 SEMICONDUCTOR STRUCTURE WITH BERYLLIUM OXIDE 有权
标题翻译：二氧化硅的半导体结构
公开(公告)号：US20140145314A1
公开(公告)日：2014-05-29
申请号：US13816164
申请日：2012-12-18
申请人： JING Wang , Renrong Liang , Lei Guo , Jun Xu
发明人： JING Wang , Renrong Liang , Lei Guo , Jun Xu
IPC分类号： H01L29/04
CPC分类号： H01L29/04 , H01L21/02381 , H01L21/02433 , H01L21/0245 , H01L21/02488 , H01L21/02507 , H01L21/02532 , H01L21/0276 , H01L21/28255 , H01L21/823807 , H01L29/06 , H01L29/1054 , H01L29/161 , H01L29/24 , H01L29/517 , H01L29/78
摘要： A semiconductor structure with beryllium oxide is provided. The semiconductor structure comprises: a semiconductor substrate (100); and a plurality of insulation oxide layers (201, 202 . . . 20x) and a plurality of single crystal semiconductor layers (301, 302 . . . 30x) alternately stacked on the semiconductor substrate (100). A material of the insulation oxide layer (201) contacted with the semiconductor substrate (100) is any one of beryllium oxide, SiO2, SiOxNy and a combination thereof, a material of other insulation oxide layers (202 . . . 20x) is single crystal beryllium oxide.
摘要翻译：提供了具有氧化铍的半导体结构。半导体结构包括：半导体衬底（100）; 以及交替层叠在半导体基板（100）上的多个绝缘氧化物层（201,202,20.0x）和多个单晶半导体层（301,302,30 ...）。与半导体衬底（100）接触的绝缘氧化物层（201）的材料是氧化铍，SiO 2，SiO x N y及其组合中的任一种，其它绝缘氧化物层（202.20x）的材料是单晶氧化铍。

15. 发明授权

US08642414B2 MOS transistor structure with in-situ doped source and drain and method for forming the same 有权
标题翻译：具有原位掺杂源极和漏极的MOS晶体管结构及其形成方法
公开(公告)号：US08642414B2
公开(公告)日：2014-02-04
申请号：US13132768
申请日：2011-01-19
申请人： Jing Wang , Lei Guo , Jun Xu
发明人： Jing Wang , Lei Guo , Jun Xu
IPC分类号： H01L21/336
CPC分类号： H01L29/1054 , H01L29/66636 , H01L29/7833 , H01L29/7848
摘要： A MOS transistor structure with an in-situ doped source and/or drain and a method for forming the same are provided. The method comprises steps of: providing a substrate; forming a high Ge content layer on the substrate; forming a gate stack on the high Ge content layer and forming a side wall of one or more layers on both sides of the gate stack; etching the high Ge content layer to form a source region and/or a drain region; and forming a source and/or a drain in the source region and/or the drain region respectively by a low-temperature selective epitaxy, and introducing a doping gas during the low-temperature selective epitaxy to heavily dope the source and/or the drain and to in-situ activate a doping element.
摘要翻译：提供具有原位掺杂源极和/或漏极的MOS晶体管结构及其形成方法。该方法包括以下步骤：提供衬底; 在所述基板上形成高Ge含量层; 在高Ge含量层上形成栅极叠层，并在栅叠层的两侧形成一层或多层的侧壁; 蚀刻高Ge含量层以形成源区和/或漏区; 以及通过低温选择性外延分别在源区和/或漏区中形成源极和/或漏极，并且在低温选择性外延期间引入掺杂气体以使源极和/或漏极并原位激活掺杂元素。

16. 发明授权

US08592864B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US08592864B2
公开(公告)日：2013-11-26
申请号：US13499661
申请日：2011-06-27
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L21/02
CPC分类号： H01L29/267 , H01L21/02381 , H01L21/0245 , H01L21/0251 , H01L21/02538 , H01L21/0262 , H01L21/02639 , H01L21/02647
摘要： A semiconductor device and a method for forming the same are provided. The semiconductor device comprises: a substrate (1); an insulating layer (2), formed on the substrate (1) and having a trench (21) to expose an upper surface of the substrate (1); a first buffer layer (3), formed on the substrate (1) and in the trench (21); and a compound semiconductor layer (4), formed on the first buffer layer (3), wherein an aspect ratio of the trench (21) is larger than 1 and smaller than 10, wherein the first buffer layer (3) is formed by a low-temperature reduced pressure chemical vapor deposition process at a temperature between 200° C. and 500° C., and wherein the compound semiconductor layer (4) is formed by a low-temperature metal organic chemical vapor deposition process at a temperature between 200° C. and 600° C.
摘要翻译：提供半导体器件及其形成方法。半导体器件包括：衬底（1）; 形成在所述基板（1）上并具有用于露出所述基板（1）的上表面的沟槽（21）的绝缘层（2）; 形成在所述基板（1）和所述沟槽（21）中的第一缓冲层（3）; 和形成在第一缓冲层（3）上的化合物半导体层（4），其中沟槽（21）的纵横比大于1且小于10，其中第一缓冲层（3）由在200℃至500℃之间的温度下进行低温减压化学气相沉积工艺，其中化合物半导体层（4）通过低温金属有机化学气相沉积工艺在200℃ ℃和600℃

17. 发明申请

US20120280274A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US20120280274A1
公开(公告)日：2012-11-08
申请号：US13499498
申请日：2011-09-07
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L29/267 , H01L21/762 , H01L21/20
CPC分类号： H01L21/02532 , H01L21/02381 , H01L21/0245 , H01L21/02513 , H01L21/02658 , H01L29/1054
摘要： A semiconductor structure is provided, comprising: a Si substrate; a porous structure layer formed on the Si substrate, in which the porous structure layer has a flat surface and comprises a Si1-xGex layer with low Ge content; and a Ge-containing layer formed on the porous structure layer, in which the Ge-containing layer comprises a Ge layer or a Si1-yGey layer with high Ge content and x≦y. Further, a method for forming the semiconductor structure is also provided.
摘要翻译：提供一种半导体结构，包括：Si衬底; 形成在Si基板上的多孔结构层，其中多孔结构层具有平坦表面并且包括具有低Ge含量的Si 1-x Ge x层; 和含Ge层，其中所述Ge含量层包含Ge层或具有高Ge含量的Si1-yGey层，x和nlE; y。此外，还提供了一种用于形成半导体结构的方法。

18. 发明申请

US20120228671A1 STRAINED GE-ON-INSULATOR STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：应变导电绝缘体结构及其形成方法
公开(公告)号：US20120228671A1
公开(公告)日：2012-09-13
申请号：US13263227
申请日：2011-08-25
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78684 , H01L29/7843 , H01L29/7846 , H01L29/7848 , H01L29/78603 , H01L29/78618
摘要： A strained Ge-on-insulator structure is provided, comprising: a silicon substrate, in which an oxide insulating layer is formed on a surface of the silicon substrate; a Ge layer formed on the oxide insulating layer, in which a first passivation layer is formed between the Ge layer and the oxide insulating layer; a gate stack formed on the Ge layer, a channel region formed below the gate stack, and a source and a drain formed on sides of the channel region; and a SiN stress cap layer covering the gate stack to produce a strain in the channel region. Further, a method for forming the strained Ge-on-insulator structure is also provided.
摘要翻译：提供了一种应变绝缘体上的结构，包括：硅衬底，其中在硅衬底的表面上形成氧化物绝缘层; 形成在所述氧化物绝缘层上的Ge层，其中在所述Ge层和所述氧化物绝缘层之间形成第一钝化层; 形成在Ge层上的栅极叠层，形成在栅叠层下方的沟道区，以及形成在沟道区的侧面上的源极和漏极; 以及覆盖栅极堆叠以在沟道区域中产生应变的SiN应力覆盖层。此外，还提供了用于形成应变的绝缘体上Ge的结构的方法。

19. 发明申请

US20120025279A1 LOW SCHOTTKY BARRIER SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME 审中-公开
标题翻译：低肖特基二极管半导体结构及其形成方法
公开(公告)号：US20120025279A1
公开(公告)日：2012-02-02
申请号：US13132760
申请日：2011-05-10
申请人： Jing Wang , Wei Wang , Lei Guo , Jun Xu
发明人： Jing Wang , Wei Wang , Lei Guo , Jun Xu
IPC分类号： H01L29/812 , H01L21/338
CPC分类号： H01L29/66636 , H01L29/0895 , H01L29/1054 , H01L29/41783 , H01L29/517 , H01L29/66477 , H01L29/66643 , H01L29/78 , H01L29/7839
摘要： A low Schottky barrier semiconductor structure is provided, comprising: a substrate; a SiGe layer with low Ge content formed on the substrate; a channel layer with high Ge content formed on the SiGe layer; a gate stack formed on the substrate and a side wall of one or more layers formed on both sides of the gate stack; a metal source and a metal drain formed in the channel layer and on the both sides of the gate stack respectively; and an insulation layer formed between the substrate and the metal source and between the substrate and the metal drain respectively.
摘要翻译：提供了一种低肖特基势垒半导体结构，包括：衬底; 在基板上形成具有低Ge含量的SiGe层; 在SiGe层上形成具有高Ge含量的沟道层; 形成在所述基板上的栅极叠层和形成在所述栅极堆叠的两侧上的一个或多个层的侧壁; 金属源和金属漏极分别形成在沟道层中和栅极堆叠的两侧; 以及分别形成在基板和金属源之间以及基板和金属引线之间的绝缘层。

20. 发明申请

US20110260173A1 SEMICONDUCTOR STRUCTURE 有权
标题翻译：半导体结构
公开(公告)号：US20110260173A1
公开(公告)日：2011-10-27
申请号：US13120122
申请日：2010-11-08
申请人： Jing Wang , Jun Xu , Lei Guo
发明人： Jing Wang , Jun Xu , Lei Guo
IPC分类号： H01L29/78
CPC分类号： H01L29/7391 , H01L29/1054 , H01L29/165 , H01L29/7833 , H01L29/785
摘要： A semiconductor structure is provided. The semiconductor structure may comprise a substrate (100); a buffer layer or an insulation layer (200) formed on the substrate; a first strained wide bandgap semiconductor material layer (400) formed on the buffer layer or the insulation layer; a strained narrow bandgap semiconductor material layer (500) formed on the first strained wide bandgap semiconductor material layer; a second strained wide bandgap semiconductor material layer (700) formed on the strained narrow bandgap semiconductor material layer; a gate stack (300) formed on the second strained wide bandgap semiconductor material layer; and a source and a drain (600) formed in the first strained wide bandgap semiconductor material layer, the strained narrow bandgap semiconductor material layer and the second strained wide bandgap semiconductor material layer respectively.
摘要翻译：提供半导体结构。半导体结构可以包括衬底（100）; 形成在所述基板上的缓冲层或绝缘层（200）; 形成在缓冲层或绝缘层上的第一应变宽带隙半导体材料层（400）形成在第一应变宽带隙半导体材料层上的应变窄带隙半导体材料层（500）形成在应变窄带隙半导体材料层上的第二应变宽带隙半导体材料层（700）形成在第二应变宽带隙半导体材料层上的栅叠层（300）以及形成在第一应变宽带隙半导体材料层中的源极和漏极（600），应变窄带隙半导体材料层和第二应变宽带隙半导体材料层。

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