会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 11. 发明授权
    • System and method for polar modulation using power amplifier bias control
    • 使用功率放大器偏置控制的极化调制系统和方法
    • US08548400B2
    • 2013-10-01
    • US11445981
    • 2006-05-31
    • Kevin B. TraylorRichard B. MeadorGeorge B. NorrisDavid S. Peckham
    • Kevin B. TraylorRichard B. MeadorGeorge B. NorrisDavid S. Peckham
    • H04B1/04
    • H03G3/3047
    • Systems and techniques are described for applying a polar bias modulation having a phase component and an amplitude component to a signal amplified by a power amplifier. The power amplifier (PA) has a plurality of amplifier gain stages and is configured to amplify an input to create an amplifier output signal. The input to the power amplitude is phase modulated based upon the phase component of the polar bias modulation, but need not be amplitude modulated. Amplitude modulation is provided by logic that includes a detector configured to receive an indication of the amplifier output as a feedback signal, a control module configured to generate a control signal based upon both the feedback signal and the amplitude component of the polar bias modulation, and a bias circuit configured to adjust a bias signal associated with at least one of the plurality of amplifier gain stages in response to the control signal. Such a modulation scheme may be readily applied in enhanced data rate for global service mode (GSM) evolution (EDGE) applications, as well as in other environments that make use of polar modulation.
    • 描述了将系统和技术应用于具有相位分量和幅度分量的极性偏置调制到由功率放大器放大的信号。 功率放大器(PA)具有多个放大器增益级,并且被配置为放大输入以产生放大器输出信号。 基于极化偏置调制的相位分量,对功率振幅的输入进行相位调制,但不需要进行幅度调制。 幅度调制由逻辑提供,逻辑包括被配置为接收放大器输出的指示作为反馈信号的检测器,控制模块被配置为基于反馈信号和极偏调制的幅度分量来产生控制信号,以及 偏置电路,被配置为响应于所述控制信号调整与所述多个放大器增益级中的至少一个相关联的偏置信号。 这种调制方案可以容易地应用于全球服务模式(GSM)演进(EDGE)应用的增强数据速率以及利用极化调制的其它环境中。
    • 12. 发明申请
    • Error correcting viterbi decoder
    • 纠正维特比解码器的错误
    • US20100011279A1
    • 2010-01-14
    • US12218183
    • 2008-07-11
    • Christopher J. BeckerKevin B. Traylor
    • Christopher J. BeckerKevin B. Traylor
    • H03M13/03G06F11/08
    • H04L1/0054H03M13/3738H03M13/3746H03M13/41H04L1/0052
    • Methods and corresponding systems in a Viterbi decoder include selecting an input symbol in an input block, wherein the input block has a plurality of input symbols, wherein each input symbol has a Boolean value, a quality value, and an associated stage, and wherein the selected symbol is selected based upon the quality value of the selected symbol relative to a quality value of other input symbols in the input block. Thereafter, the Boolean value of the selected symbol is complemented to produce a complemented symbol. The complemented symbol is substituted for the selected symbol to produce an alternate input block. A Viterbi algorithm is executed using the alternate input block to produce an alternate decoded bit sequence, which is then checked for errors using an error check. The alternate decoded bit sequence is output in response to the alternate decoded bit sequence passing the error check.
    • 维特比解码器中的方法和对应系统包括选择输入块中的输入符号,其中输入块具有多个输入符号,其中每个输入符号具有布尔值,质量值和相关级,并且其中 基于所选符号的质量值相对于输入块中的其他输入符号的质量值来选择所选择的符号。 此后,补充所选符号的布尔值以产生补码。 替代了所选符号以产生替代输入块。 使用替代输入块执行维特比算法来产生替代解码比特序列,然后使用错误检查来检查错误。 响应于通过错误检查的替代解码比特序列输出替代解码比特序列。
    • 13. 发明申请
    • System and method for polar modulation using power amplifier bias control
    • 使用功率放大器偏置控制的极化调制系统和方法
    • US20070290747A1
    • 2007-12-20
    • US11445981
    • 2006-05-31
    • Kevin B. TraylorRichard B. MeadorGeorge B. NorrisDavid S. Peckham
    • Kevin B. TraylorRichard B. MeadorGeorge B. NorrisDavid S. Peckham
    • H03G5/16
    • H03G3/3047
    • Systems and techniques are described for applying a polar bias modulation having a phase component and an amplitude component to a signal amplified by a power amplifier. The power amplifier (PA) has a plurality of amplifier gain stages and is configured to amplify an input to create an amplifier output signal. The input to the power amplitude is phase modulated based upon the phase component of the polar bias modulation, but need not be amplitude modulated. Amplitude modulation is provided by logic that includes a detector configured to receive an indication of the amplifier output as a feedback signal, a control module configured to generate a control signal based upon both the feedback signal and the amplitude component of the polar bias modulation, and a bias circuit configured to adjust a bias signal associated with at least one of the plurality of amplifier gain stages in response to the control signal. Such a modulation scheme may be readily applied in enhanced data rate for global service mode (GSM) evolution (EDGE) applications, as well as in other environments that make use of polar modulation.
    • 描述了将系统和技术应用于具有相位分量和幅度分量的极性偏置调制到由功率放大器放大的信号。 功率放大器(PA)具有多个放大器增益级,并且被配置为放大输入以产生放大器输出信号。 基于极化偏置调制的相位分量,对功率振幅的输入进行相位调制,但不需要进行幅度调制。 幅度调制由逻辑提供,逻辑包括被配置为接收放大器输出的指示作为反馈信号的检测器,控制模块被配置为基于反馈信号和极偏调制的幅度分量来产生控制信号,以及 偏置电路,被配置为响应于所述控制信号调整与所述多个放大器增益级中的至少一个相关联的偏置信号。 这种调制方案可以容易地应用于全球服务模式(GSM)演进(EDGE)应用的增强数据速率以及利用极化调制的其它环境中。
    • 14. 发明授权
    • Techniques for performing discrete fourier transforms on radix-2 platforms
    • 在基数2平台上进行离散傅里叶变换的技术
    • US08271569B2
    • 2012-09-18
    • US12140890
    • 2008-06-17
    • Jayakrishnan C. MundarathLeo G. DehnerKevin B. Traylor
    • Jayakrishnan C. MundarathLeo G. DehnerKevin B. Traylor
    • G06F15/00
    • G06F17/142
    • A technique for performing a discrete Fourier transform (DFT) includes storing, in a single-port memory, multiple signal points. A first group of consecutive ones of the multiple signal points are fetched (from a first line of the single-port memory) to a first input register associated with a processor that includes multiple arithmetic units (AUs) that are each configured to perform multiply accumulate (MAC) operations. A second group of consecutive ones of the multiple signal points are then fetched (from a second line of the single-port memory) to a second input register associated with the processor. Selected pairs of the multiple signal points are then loaded (one from each of the first and second input registers for each pair) into the multiple arithmetic units during an initial butterfly stage. Radix-2 butterfly operations are then performed on the selected pairs of the multiple signal points (using the multiple AUs) to provide respective output elements.
    • 用于执行离散傅里叶变换(DFT)的技术包括在单端口存储器中存储多个信号点。 将多个信号点中的连续的多个信号点中的第一组(从单端口存储器的第一行)提取到与包括多个运算单元(AU)的处理器相关联的第一输入寄存器,每个运算单元被配置为执行乘法累积 (MAC)操作。 然后将多个信号点中的第二组连续的信号点从单端口存储器的第二行提取到与处理器相关联的第二输入寄存器。 然后,在初始蝴蝶阶段期间,将多个信号点的所选择的对加载(每对中的每个第一和第二输入寄存器中的一个)分配到多个运算单元中。 然后对所选择的多个信号点对(使用多个AU)执行基2蝶形运算,以提供相应的输出元件。