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11. 发明申请

US20080200021A1 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 失效
标题翻译：分散多晶硅/多晶硅合金栅极堆叠
公开(公告)号：US20080200021A1
公开(公告)日：2008-08-21
申请号：US12104570
申请日：2008-04-17
申请人： Kevin K. Chan , Jia Chen , Shih-Fen Huang , Edward J. Nowak
发明人： Kevin K. Chan , Jia Chen , Shih-Fen Huang , Edward J. Nowak
IPC分类号： H01L21/3205
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4A厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

12. 发明申请

US20060105523A1 Chemical doping of nano-components 失效
公开(公告)号：US20060105523A1
公开(公告)日：2006-05-18
申请号：US10991582
申请日：2004-11-18
申请人： Ali Afzali-Ardakani , Phaedon Avouris , Jia Chen , Christian Klinke , Christopher Murray , Dmitri Talapin
发明人： Ali Afzali-Ardakani , Phaedon Avouris , Jia Chen , Christian Klinke , Christopher Murray , Dmitri Talapin
IPC分类号： H01L21/336
CPC分类号： H01L21/22 , B82Y10/00 , H01L51/002 , H01L51/0048 , Y10S977/742 , Y10S977/938
摘要： A method is provided for doping nano-components, including nanotubes, nanocrystals and nanowires, by exposing the nano-components to an organic amine-containing dopant. A method is also provided for forming a field effect transistor comprising a nano-component that has been doped using such a dopant.

13. 发明申请

US20050199906A1 Split poly-SiGe/poly-Si alloy gate stack 有权
标题翻译：分离多晶硅/多晶硅合金栅叠层
公开(公告)号：US20050199906A1
公开(公告)日：2005-09-15
申请号：US11124978
申请日：2005-05-09
申请人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
发明人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
IPC分类号： H01L20060101 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L29/24 , H01L29/49 , H01L29/76 , H01L31/072 , H01L31/119
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

14. 发明申请

US20050073014A1 Split poly-SiGe/poly-Si alloy gate stack 有权
标题翻译：分离多晶硅/多晶硅合金栅叠层
公开(公告)号：US20050073014A1
公开(公告)日：2005-04-07
申请号：US10680820
申请日：2003-10-07
申请人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
发明人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
IPC分类号： H01L20060101 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L29/24 , H01L29/49 , H01L29/76 , H01L31/072 , H01L31/119
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧环境中原位吹扫沉积室导致3至4厚度的薄SiO 2或SixGeyOz界面层。薄的SiO 2或SixGeyOz界面层是足够薄且不连续的，以提供对栅极电流的很小的阻力，但是具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散，从而允许随后沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

15. 发明授权

US06828181B2 Dual gate material process for CMOS technologies 失效
标题翻译：用于CMOS技术的双栅极材料工艺
公开(公告)号：US06828181B2
公开(公告)日：2004-12-07
申请号：US10249800
申请日：2003-05-08
申请人： Jia Chen , Andreas E. Grassmann
发明人： Jia Chen , Andreas E. Grassmann
IPC分类号： H01L218238
CPC分类号： H01L21/823842
摘要： A method and structure for a method of manufacturing a device having different types of transistors, wherein gates of the different types of transistors in the device comprise different materials. The method comprises depositing a silicon layer on a gate dielectric layer, depositing a first-type gate material on the silicon layer, removing the first-type gate material from areas where a second-type gate is to be formed, depositing a second-type gate material on the silicon layer in areas where the first-type gate material was removed, and simultaneously patterning the first-type gate material and the second-type gate material into first-type and second-type gates, and anneal and transform the two types of gate materials.
摘要翻译：用于制造具有不同类型晶体管的器件的方法的方法和结构，其中器件中不同类型的晶体管的栅极包括不同的材料。该方法包括在栅极电介质层上沉积硅层，在硅层上沉积第一种类型的栅极材料，从要形成第二类型栅极的区域去除第一种类型的栅极材料; 在去除了第一种类型的栅极材料的区域中的硅层上的栅极材料，同时将第一种栅极材料和第二种栅极材料构图成第一类型和第二种栅极，并且对两种栅极材料进行退火和变换门材料种类。

16. 发明申请

US20130054583A1 PERSONALIZING SCOPING AND ORDERING OF OBJECT TYPES FOR SEARCH 有权
标题翻译：个性化搜索和搜索对象类型的排序
公开(公告)号：US20130054583A1
公开(公告)日：2013-02-28
申请号：US13465851
申请日：2012-05-07
申请人： Walter Macklem , David Nathanson , Jia Chen , Luke Ball , Shankara B. Subramanya , Kanishka Maheshwari , Susan Kimberlin
发明人： Walter Macklem , David Nathanson , Jia Chen , Luke Ball , Shankara B. Subramanya , Kanishka Maheshwari , Susan Kimberlin
IPC分类号： G06F17/30
CPC分类号： G06F17/3053 , G06F17/30312 , G06F17/30867
摘要： A method of establishing personalized limits on a search responsive to a key word query in an enterprise search system is described that includes receiving an object types access history for a particular user. Applying this method, the object types access history includes records of object types selected from search results returning multiple object types and records of object types selected via interfaces other than search results. The method continues with determining and storing in computer readable memory a personalized scope of object types. The personalized scope of object types sets a limit on object types initially returned by an enterprise search system for the particular user in response to key word queries by the particular user that do not specify object types to search.
摘要翻译：描述了响应于企业搜索系统中的关键字查询来搜索关于搜索的个性化限制的方法，其包括接收特定用户的对象类型访问历史。应用此方法，对象类型访问历史记录包括从搜索结果中选择的对象类型的记录，返回多个对象类型，以及通过除搜索结果之外的界面选择的对象类型的记录。该方法继续确定和存储在计算机可读存储器中的对象类型的个性化范围。对象类型的个性化范围对特定用户最初由企业搜索系统返回的对象类型设置限制，以响应特定用户对不指定要搜索的对象类型的关键词查询。

17. 发明授权

US07872334B2 Carbon nanotube diodes and electrostatic discharge circuits and methods 有权
标题翻译：碳纳米管二极管和静电放电电路及方法
公开(公告)号：US07872334B2
公开(公告)日：2011-01-18
申请号：US11744234
申请日：2007-05-04
申请人： Jia Chen , Steven Howard Voldman
发明人： Jia Chen , Steven Howard Voldman
IPC分类号： H01L51/30
CPC分类号： H01L51/0583 , B82Y10/00 , H01L27/0255 , H01L51/0048 , Y10S977/75
摘要： Diodes and method of fabricating diodes. A diode includes: an p-type single wall carbon nanotube; an n-type single wall carbon nanotube, the p-type single wall carbon nanotube in physical and electrical contact with the n-type single wall carbon nanotube; and a first metal pad in physical and electrical contact with the p-type single wall carbon nanotube and a second metal pad in physical and electrical contact with the n-type single wall carbon nanotube.
摘要翻译：二极管和制造二极管的方法。二极管包括：p型单壁碳纳米管; n型单壁碳纳米管，p型单壁碳纳米管与n型单壁碳纳米管物理和电接触; 以及与p型单壁碳纳米管物理和电接触的第一金属焊盘和与n型单壁碳纳米管物理和电接触的第二金属焊盘。

18. 发明授权

US07598516B2 Self-aligned process for nanotube/nanowire FETs 有权
标题翻译：纳米管/纳米线FET的自对准工艺
公开(公告)号：US07598516B2
公开(公告)日：2009-10-06
申请号：US11031168
申请日：2005-01-07
申请人： Phaedon Avouris , Roy A. Carruthers , Jia Chen , Christophe G. M. M. Detavernier , Christian Lavoie , Hon-Sum Philip Wong
发明人： Phaedon Avouris , Roy A. Carruthers , Jia Chen , Christophe G. M. M. Detavernier , Christian Lavoie , Hon-Sum Philip Wong
IPC分类号： H01L29/775 , H01L29/06
CPC分类号： H01L29/6656 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/665 , H01L29/7833 , H01L51/0048 , H01L51/0541 , Y10S977/847 , Y10S977/938
摘要： A complementary metal oxide semiconductor (CMOS) device, e.g., a field effect transistor (FET), that includes at least one one-dimensional nanostructure that is typically a carbon-based nanomaterial, as the device channel, and a metal carbide contact that is self-aligned with the gate region of the device is described. The present invention also provides a method of fabricating such a CMOS device.
摘要翻译：互补金属氧化物半导体（CMOS）器件，例如场效应晶体管（FET），其包括通常为碳基纳米材料的至少一个一维纳米结构作为器件沟道，以及金属碳化物接触描述与设备的栅极区域自对准的步骤。本发明还提供一种制造这种CMOS器件的方法。

19. 发明申请

US20080273280A1 Carbon Nanotube Diodes And Electrostatic Discharge Circuits And Methods 有权
标题翻译：碳纳米管二极管和静电放电电路及方法
公开(公告)号：US20080273280A1
公开(公告)日：2008-11-06
申请号：US11744234
申请日：2007-05-04
申请人： Jia Chen , Steven Howard Voldman
发明人： Jia Chen , Steven Howard Voldman
IPC分类号： H01L29/06 , H02H9/04
CPC分类号： H01L51/0583 , B82Y10/00 , H01L27/0255 , H01L51/0048 , Y10S977/75
摘要： Diodes and method of fabricating diodes. A diode includes: an p-type single wall carbon nanotube; an n-type single wall carbon nanotube, the p-type single wall carbon nanotube in physical and electrical contact with the n-type single wall carbon nanotube; and a first metal pad in physical and electrical contact with the p-type single wall carbon nanotube and a second metal pad in physical and electrical contact with the n-type single wall carbon nanotube.
摘要翻译：二极管和制造二极管的方法。二极管包括：p型单壁碳纳米管; n型单壁碳纳米管，p型单壁碳纳米管与n型单壁碳纳米管物理和电接触; 以及与p型单壁碳纳米管物理和电接触的第一金属焊盘和与n型单壁碳纳米管物理和电接触的第二金属焊盘。

20. 发明申请

US20080246120A1 REDUCTION OF SILICIDE FORMATION TEMPERATURE ON SiGe CONTAINING SUBSTRATES 有权
标题翻译：在含SiGe衬底上减少硅化物形成温度
公开(公告)号：US20080246120A1
公开(公告)日：2008-10-09
申请号：US12120854
申请日：2008-05-15
申请人： Cyril Cabral , Roy A. Carruthers , Jia Chen , Christophe Detavernier , James M. Harper , Christian Lavoie
发明人： Cyril Cabral , Roy A. Carruthers , Jia Chen , Christophe Detavernier , James M. Harper , Christian Lavoie
IPC分类号： H01L29/161
CPC分类号： H01L21/28518
摘要： A method that solves the increased nucleation temperature that is exhibited during the formation of cobalt disilicides in the presence of Ge atoms is provided. The reduction in silicide formation temperature is achieved by first providing a structure including a Co layer including at least Ni, as an additive element, on top of a SiGe containing substrate. Next, the structure is subjected to a self-aligned silicide process which includes a first anneal, a selective etching step and a second anneal to form a solid solution of (Co, Ni) disilicide on the SiGe containing substrate. The Co layer including at least Ni can comprise an alloy layer of Co and Ni, a stack of Ni/Co or a stack of Co/Ni. A semiconductor structure including the solid solution of (Co, Ni) disilicide on the SiGe containing substrate is also provided.
摘要翻译：提供了一种解决在锗原子存在下形成二硅化钴期间显示的增加的成核温度的方法。硅化物形成温度的降低通过首先提供包括至少包含Ni的Co层作为添加元素在包含SiGe的衬底的顶部上的结构来实现。接下来，对该结构进行自对准硅化物工艺，其包括第一退火，选择性蚀刻步骤和第二退火，以在含SiGe的衬底上形成（Co，Ni）二硅化物的固溶体。至少包括Ni的Co层可以包括Co和Ni的合金层，Ni / Co的堆叠或Co / Ni的堆叠。还提供了包含（Co，Ni）二硅化物在含SiGe的衬底上的固溶体的半导体结构。

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