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11. 发明申请

US20070165035A1 DEFERRED SHADING GRAPHICS PIPELINE PROCESSOR HAVING ADVANCED FEATURES 有权
标题翻译：具有先进功能的缩减图形管道处理器
公开(公告)号：US20070165035A1
公开(公告)日：2007-07-19
申请号：US11613093
申请日：2006-12-19
申请人： Jerome Duluk , Richard Hessel , Vaughn Arnold , Jack Benkual , Joseph Bratt , George Cuan , Stephen Dodgen , Emerson Fang , Zhaoyu Gong , Thomas Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew Papakipos , Jason Redgrave , Sushma Trivedi , Nathan Tuck , Shun Go , Lindy Fung , Tuan Nguyen , Joseph Grass , Bo Hung , Abraham Mammen , Abbas Rashid , Albert Tsay
发明人： Jerome Duluk , Richard Hessel , Vaughn Arnold , Jack Benkual , Joseph Bratt , George Cuan , Stephen Dodgen , Emerson Fang , Zhaoyu Gong , Thomas Ho , Hengwei Hsu , Sidong Li , Sam Ng , Matthew Papakipos , Jason Redgrave , Sushma Trivedi , Nathan Tuck , Shun Go , Lindy Fung , Tuan Nguyen , Joseph Grass , Bo Hung , Abraham Mammen , Abbas Rashid , Albert Tsay
IPC分类号： G06T1/20
CPC分类号： G06T15/20 , G06T1/60 , G06T11/001 , G06T11/40 , G06T15/005 , G06T15/04 , G06T15/30 , G06T15/40 , G06T15/50 , G06T15/80 , G06T15/83 , G06T15/87
摘要： A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.
摘要翻译：提供了包括许多子结构的延迟着色图形流水线处理器和方法。处理器和方法的实施例可以包括延迟着色，平铺帧缓冲器和多级隐藏表面去除处理中的一个或多个。在延迟阴影图形管道中，在完成像素着色之前完成隐藏表面移除。流水线处理器包括命令提取和解码单元，几何单元，模式提取单元，分类单元，设置单元，剔除单元，模式注入单元，片段单元，纹理单元，Phong照明单元，像素单元和后端单元。

12. 发明授权

US5502406A Low power level shift circuit and method therefor 失效
标题翻译：低功率电平移位电路及其方法
公开(公告)号：US5502406A
公开(公告)日：1996-03-26
申请号：US399004
申请日：1995-03-06
申请人： Kevin M. Traynor , Hengwei Hsu
发明人： Kevin M. Traynor , Hengwei Hsu
IPC分类号： H03K19/00 , H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018521 , H03K19/0013
摘要： A low power level shift and buffer circuit (40) is used to level shift and amplify an output of an oscillator (14, 16, 18, 20, 22, 24) in a data processing application (10). A current mirror (58) and a reference current are used to provide a constant current source load for an inverter (56, 42). Separate controls for each of the two transistors forming a push/pull inverter (54, 50) eliminate a switching transient current by providing non-overlapping inputs to each of the two transistors. By eliminating the switching transient current, little power is consumed during the level shifting and amplification process. Furthermore, a significant amount of circuit area is not required and an output with fast rise and fall times is provided.
摘要翻译：低功率电平移位和缓冲电路（40）用于对数据处理应用（10）中的振荡器（14,16,18,20,22,24）的输出进行电平移位和放大。使用电流镜58和参考电流为逆变器（56,42）提供恒定电流源负载。形成推/拉逆变器（54,50）的两个晶体管中的每一个的单独控制通过向两个晶体管中的每一个提供非重叠的输入来消除开关瞬态电流。通过消除开关瞬态电流，在电平转换和放大过程中消耗的功率很小。此外，不需要大量的电路面积，并且提供具有快速上升和下降时间的输出。

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