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11. 发明授权

US07568070B2 Instruction cache having fixed number of variable length instructions 有权
标题翻译：指令缓存具有固定数量的可变长度指令
公开(公告)号：US07568070B2
公开(公告)日：2009-07-28
申请号：US11193547
申请日：2005-07-29
申请人： Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith , Thomas Andrew Sartorius
发明人： Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith , Thomas Andrew Sartorius
IPC分类号： G06F9/34
CPC分类号： G06F9/30149 , G06F9/3816 , G06F9/382
摘要： A fixed number of variable-length instructions are stored in each line of an instruction cache. The variable-length instructions are aligned along predetermined boundaries. Since the length of each instruction in the line, and hence the span of memory the instructions occupy, is not known, the address of the next following instruction is calculated and stored with the cache line. Ascertaining the instruction boundaries, aligning the instructions, and calculating the next fetch address are performed in a predecoder prior to placing the instructions in the cache.
摘要翻译：固定数量的可变长度指令存储在指令高速缓存的每一行中。可变长度指令沿预定边界排列。由于行中的每条指令的长度以及指令占用的存储器的跨度是未知的，所以下一个跟随指令的地址被计算并与高速缓存行一起存储。在将指令置于高速缓存之前，确定指令边界，对准指令并计算下一个提取地址在预解码器中执行。

12. 发明授权

US07426626B2 TLB lock indicator 有权
标题翻译： TLB锁定指示灯
公开(公告)号：US07426626B2
公开(公告)日：2008-09-16
申请号：US11210526
申请日：2005-08-23
申请人： Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/126 , G06F2212/681
摘要： A processor includes a hierarchical Translation Lookaside Buffer (TLB) comprising a Level-1 TLB and a small, high-speed Level-0 TLB. Entries in the L0 TLB replicate entries in the L1 TLB. The processor first accesses the L0 TLB in an address translation, and access the L1 TLB if a virtual address misses in the L0 TLB. When the virtual address hits in the L1 TLB, the virtual address, physical address, and page attributes are written to the L0 TLB, replacing an existing entry if the L0 TLB is full. The entry may be locked against replacement in the L0 TLB in response to an L0 Lock (L0L) indicator in the L1 TLB entry. Similarly, in a hardware-managed L1 TLB, entries may be locked against replacement in response to an L1 Lock (L1L) indicator in the corresponding page table entry.
摘要翻译：处理器包括包括Level-1 TLB和小的高速Level-0 TLB的分级翻译后备缓冲器（TLB）。 L0 TLB中的条目复制L1 TLB中的条目。处理器首先在地址转换中访问L0 TLB，如果在L0 TLB中虚拟地址丢失，则访问L1 TLB。当虚拟地址在L1 TLB中时，虚拟地址，物理地址和页面属性被写入L0 TLB，如果L0 TLB已满，则替换现有的条目。响应于L1 TLB条目中的L0锁定（L0L）指示灯，该条目可能被锁定在L0 TLB中。类似地，在硬件管理的L1 TLB中，可以响应于相应页表条目中的L1锁定（L1L）指示符来锁定条目以替代。

13. 发明授权

US07415638B2 Pre-decode error handling via branch correction 有权
标题翻译：通过分支校正预解码错误处理
公开(公告)号：US07415638B2
公开(公告)日：2008-08-19
申请号：US10995858
申请日：2004-11-22
申请人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F11/00 , G06F9/30
CPC分类号： G06F9/3861 , G06F9/30152 , G06F9/3017 , G06F9/382
摘要： In a pipelined processor where instructions are pre-decoded prior to being stored in a cache, an incorrectly pre-decoded instruction is detected during execution in the pipeline. The corresponding instruction is invalidated in the cache, and the instruction is forced to evaluate as a branch instruction. In particular, the branch instruction is evaluated as “mispredicted not taken” with a branch target address of the incorrectly pre-decoded instruction's address. This, with the invalidated cache line, causes the incorrectly pre-decoded instruction to be re-fetched from memory with a precise address. The re-fetched instruction is then correctly pre-decoded, written to the cache, and executed.
摘要翻译：在流水线处理器中，在将存储在高速缓存中的指令进行预解码之前，在流水线执行期间检测到未正确预解码的指令。相应的指令在缓存中无效，并且强制将该指令作为分支指令进行求值。特别地，分支指令被评估为未被错误地预解码的指令的地址的分支目标地址“未被采用”。这使得无效的高速缓存行导致错误地预解码的指令从具有精确地址的存储器重新获取。然后重新获取的指令被正确预解码，写入高速缓存并执行。

14. 发明授权

US07278012B2 Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions 有权
标题翻译：用于有效地访问第一和第二分支历史表以预测分支指令的方法和装置
公开(公告)号：US07278012B2
公开(公告)日：2007-10-02
申请号：US11144206
申请日：2005-06-02
申请人： Thomas Andrew Sartorius , Brian Michael Stempel , Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Brian Michael Stempel , Jeffrey Todd Bridges , James Norris Dieffenderfer , Rodney Wayne Smith
IPC分类号： G06F9/42
CPC分类号： G06F9/3844
摘要： A microprocessor includes two branch history tables, and is configured to use a first one of the branch history tables for predicting branch instructions that are hits in a branch target cache, and to use a second one of the branch history tables for predicting branch instructions that are misses in the branch target cache. As such, the first branch history table is configured to have an access speed matched to that of the branch target cache, so that its prediction information is timely available relative to branch target cache hit detection, which may happen early in the microprocessor's instruction pipeline. The second branch history table thus need only be as fast as is required for providing timely prediction information in association with recognizing branch target cache misses as branch instructions, such as at the instruction decode stage(s) of the instruction pipeline.
摘要翻译：微处理器包括两个分支历史表，并且被配置为使用第一个分支历史表来预测分支目标高速缓存中的命中的分支指令，并且使用第二个分支历史表来预测分支指令，在分支目标缓存中丢失。因此，第一分支历史表被配置为具有与分支目标高速缓存的访问速度匹配的访问速度，使得其预测信息相对于可能在微处理器的指令流水线的早期发生的分支目标高速缓存命中检测而及时可用。因此，第二分支历史表仅需要与将识别分支目标高速缓存未命中作为分支指令（例如在指令流水线的指令解码阶段）相关联地提供及时的预测信息所需的速度。

15. 发明授权

US07203826B2 Method and apparatus for managing a return stack 有权
标题翻译：用于管理返回堆栈的方法和装置
公开(公告)号：US07203826B2
公开(公告)日：2007-04-10
申请号：US11061975
申请日：2005-02-18
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/4486
摘要： A processor includes a return stack circuit used for predicting procedure return addresses for instruction pre-fetching, wherein a return stack controller determines the number of return levels associated with a given return instruction, and pops that number of return addresses from the return stack. Popping multiple return addresses from the return stack permits the processor to pre-fetch the return address of the original calling procedure in a chain of successive procedure calls. In one embodiment, the return stack controller reads the number of return levels from a value embedded in the return instruction. A complementary compiler calculates the return level values for given return instructions and embeds those values in them at compile-time. In another embodiment, the return stack circuit dynamically tracks the number of return levels by counting the procedure calls (branches) in a chain of successive procedure calls.
摘要翻译：处理器包括用于预测用于指令预取的过程返回地址的返回堆栈电路，其中返回堆栈控制器确定与给定返回指令相关联的返回电平的数量，并且从返回堆栈中弹出该返回地址的数量。从返回堆栈弹出多个返回地址允许处理器在连续的过程调用链中预取原始调用过程的返回地址。在一个实施例中，返回堆栈控制器从嵌入在返回指令中的值读取返回电平的数量。补充编译器计算给定返回指令的返回值，并在编译时嵌入这些值。在另一个实施例中，返回堆栈电路通过对连续过程调用链中的过程调用（分支）进行计数来动态地跟踪返回电平的数量。

16. 发明申请

US20080177992A1 Segmented Pipeline Flushing for Mispredicted Branches 有权
标题翻译：分段管道冲洗用于预测分支
公开(公告)号：US20080177992A1
公开(公告)日：2008-07-24
申请号：US11626443
申请日：2007-01-24
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Michael Scott McIlvaine , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Michael Scott McIlvaine , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3842 , G06F9/3863 , G06F9/3867
摘要： A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.
摘要翻译：处理器管线在分配给程序顺序之外的指令之前被分割成上部，并且超出上部的一个或多个下部。在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。较低的管道可以继续执行，直到错误预测的分支指令确认，此时所有未提交的指令都从较低管道冲洗。可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。

17. 发明授权

US07650466B2 Method and apparatus for managing cache partitioning using a dynamic boundary 有权
标题翻译：使用动态边界管理缓存分区的方法和装置
公开(公告)号：US07650466B2
公开(公告)日：2010-01-19
申请号：US11233575
申请日：2005-09-21
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译：管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。响应于解锁写入，第二个指针是高级的。第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。

18. 发明授权

US07454538B2 Latency insensitive FIFO signaling protocol 有权
标题翻译：延迟不敏感的FIFO信令协议
公开(公告)号：US07454538B2
公开(公告)日：2008-11-18
申请号：US11128135
申请日：2005-05-11
申请人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
发明人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
IPC分类号： G06F3/00
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。源端计数器跟踪FIFO中可用的空间。在公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。响应于来自接收器域的信令从FIFO读取数据，计数器递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

19. 发明申请

US20080281996A1 Latency Insensitive FIFO Signaling Protocol 有权
标题翻译：延迟不敏感的FIFO信令协议
公开(公告)号：US20080281996A1
公开(公告)日：2008-11-13
申请号：US12179970
申请日：2008-07-25
申请人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
发明人： Kenneth Alan Dockser , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Robert Douglas Clancy , Thomas Andrew Sartorius
IPC分类号： G06F13/38 , G06F3/00
CPC分类号： G06F13/4059 , G06F5/06 , G06F2205/126
摘要： Data from a source domain operating at a first data rate is transferred to a FIFO in another domain operating at a different data rate. The FIFO buffers data before transfer to a sink for further processing or storage. A source side counter tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter decrements in response to a data ready signal from the source domain, without delay. The counter increments in response to signaling from the sink domain of a read of data off the FIFO. Hence, incrementing is subject to the signaling latency between domains. The source may send one more beat of data when the counter indicates the FIFO is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one more FIFO position.
摘要翻译：来自以第一数据速率运行的源域的数据被传送到以不同数据速率工作的另一个域中的FIFO。 FIFO在传输到宿之前缓冲数据以进一步处理或存储。源端计数器跟踪FIFO中可用的空间。在公开的示例中，初始计数器值对应于FIFO深度。响应于来自源域的数据就绪信号，计数器无延迟地递减。响应于来自接收器域的信令从FIFO读取数据，计数器递增。因此，增量受到域之间的信令等待时间的限制。当计数器指示FIFO已满时，源可能再发送一次数据。数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个FIFO位置。

20. 发明授权

US07376815B2 Methods and apparatus to insure correct predecode 有权
标题翻译：确保正确预解码的方法和装置
公开(公告)号：US07376815B2
公开(公告)日：2008-05-20
申请号：US11066957
申请日：2005-02-25
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius
IPC分类号： G06F9/30
CPC分类号： G06F9/30149 , G06F8/447 , G06F9/382
摘要： Techniques for ensuring a synchronized predecoding of an instruction string are disclosed. The instruction string contains instructions from a variable length instruction set and embedded data. One technique includes defining a granule to be equal to the smallest length instruction in the instruction set and defining the number of granules that compose the longest length instruction in the instruction set to be MAX. The technique further includes determining the end of an embedded data segment, when a program is compiled or assembled into the instruction string and inserting a padding of length, MAX−1, into the instruction string to the end of the embedded data. Upon predecoding of the padded instruction string, a predecoder maintains synchronization with the instructions in the padded instruction string even if embedded data is coincidentally encoded to resemble an existing instruction in the variable length instruction set.
摘要翻译：公开了用于确保指令串的同步预解码的技术。指令串包含来自可变长度指令集和嵌入数据的指令。一种技术包括定义一个等于指令集中最小长度指令的粒子，并将构成指令集中最长指令的粒子数定义为MAX。该技术还包括当程序被编译或组装成指令串并将长度为MAX-1的填充插入到嵌入数据的结尾的指令串中时，确定嵌入数据段的结束。在预编译填充指令串时，即使嵌入数据被巧合地编码成类似于可变长度指令集中的现有指令，预解码器也保持与填充指令串中的指令的同步。

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