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11. 发明申请

US20080079158A1 METAL FILL REGION OF A SEMICONDUCTOR CHIP 失效
标题翻译：金属填充区半导体芯片
公开(公告)号：US20080079158A1
公开(公告)日：2008-04-03
申请号：US11538118
申请日：2006-10-03
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： H01L23/52
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：公开了一种半导体芯片的金属填充区域，其包括半导体芯片的多个层组，每组包括设置在彼此平行的平面中的第一金属填充层，第二金属填充层和绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴与任何参考点垂直地相交于所述金属填充层的平面和绝缘层，以及金属填充图案，被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在与所述金属填充轴中的每一个垂直的至少一个方向上在所述第二金属填充层中的每个片的轴线线性位移。

12. 发明授权

US06365934B1 Method and apparatus for elimination of parasitic bipolar action in complementary oxide semiconductor (CMOS) silicon on insulator (SOI) circuits 失效
标题翻译：用于消除互补氧化物半导体（CMOS）绝缘体上硅（SOI）电路中的寄生双极作用的方法和装置
公开(公告)号：US06365934B1
公开(公告)日：2002-04-02
申请号：US09240244
申请日：1999-01-29
申请人： Salvatore N. Storino , Andrew Douglas Davies
发明人： Salvatore N. Storino , Andrew Douglas Davies
IPC分类号： H03K19096
CPC分类号： H01L27/0266
摘要： The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.
摘要翻译：本发明是一种用于消除绝缘体上硅（SOI）金属氧化物半导体（MOS）器件中的寄生双极晶体管作用的装置和方法。根据本发明，提供耦合到所述SOI电子器件的SOI电子器件和有源放电器件以去激活寄生双极晶体管。通过控制有源放电装置的导通来使寄生双极晶体管的动作失效，所述有源放电装置耦合到所述SOI装置。

13. 发明授权

US6163173A Method and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performance 失效
标题翻译：用于在动态电路中实现可调逻辑门限的方法和装置，以最大化电路性能
公开(公告)号：US6163173A
公开(公告)日：2000-12-19
申请号：US305704
申请日：1999-05-05
申请人： Salvatore N. Storino , Gregory John Uhlmann , Robert Russell Williams
发明人： Salvatore N. Storino , Gregory John Uhlmann , Robert Russell Williams
IPC分类号： H03K19/00 , H03K19/096 , H03K19/96
CPC分类号： H03K19/0963 , H03K19/0027
摘要： Methods and apparatus are provided for implementing adjustable logic threshold in dynamic circuits. The dynamic circuit includes an intermediate precharge node. An output logic stage is connected to the intermediate precharge node. A threshold adjustment circuit is connected to the output logic stage. The threshold adjustment circuit receives a selection input to adjust a threshold of the output logic stage. The threshold adjustment circuit is formed of a first transistor and a second transistor coupled in parallel with a pair of series connected transistors included in the output logic stage. One or both of the first transistor and second transistor are selectively activated to adjust the threshold of the output logic stage.
摘要翻译：提供了用于在动态电路中实现可调逻辑阈值的方法和装置。动态电路包括中间预充电节点。输出逻辑级连接到中间预充电节点。阈值调整电路连接到输出逻辑级。阈值调整电路接收选择输入以调整输出逻辑级的阈值。阈值调节电路由与输出逻辑级中包括的一对串联连接的晶体管并联耦合的第一晶体管和第二晶体管构成。选择性地激活第一晶体管和第二晶体管中的一个或两个以调整输出逻辑级的阈值。

14. 发明申请

US20080266246A1 TRAVERSING GRAPHICAL LAYERS USING A SCROLLING MECHANISM IN A PHYSICAL DESIGN ENVIRONMENT 审中-公开
标题翻译：在物理设计环境中使用滚动机构处理图形层
公开(公告)号：US20080266246A1
公开(公告)日：2008-10-30
申请号：US11739911
申请日：2007-04-25
申请人： Karl L. Ladin , Chun-Tao Li , Salvatore N. Storino
发明人： Karl L. Ladin , Chun-Tao Li , Salvatore N. Storino
IPC分类号： G06F3/048 , G06F15/00 , G09G5/08
CPC分类号： G06F3/0485
摘要： Z-axis display navigation in the design automation process of physical design, development and manufacturing of integrated circuits includes pre-selecting, using a computer mouse connected to a computer workstation processor, viewable graphical layout layers desired by a design layout debugging operator to view during an integrated circuit (IC) design debugging process. After selecting the desired viewable graphic layout layers, the layout operator uses the mouse to traverse the pre-selected viewable graphical layout layers displayed, by changing the input scrolling pattern of the mouse to scroll forward, backward, diagonally and from side to side in a plurality of directions, where a curser on the layout screen will correspondingly move in the plurality of directions in the pre-selected viewable graphical layout layers on the layout screen corresponding to the movement of the mouse by the operator.
摘要翻译： Z轴显示导航在设计自动化过程中的物理设计，开发和制造集成电路包括预先选择，使用连接到计算机工作站处理器的计算机鼠标，通过设计布局调试操作员所需的可见图形布局层来查看集成电路（IC）设计调试过程。在选择所需的可见图形布局图层之后，布局运算符通过改变鼠标的输入滚动模式来滚动向前，向后，向对角和从一侧到另一侧，使用鼠标遍历预先选择的可视图形布局图层。多个方向，其中布局屏幕上的卷曲器将相应地在布局屏幕上的预选择的可视图形布局层中的多个方向上移动，对应于操作者对鼠标的移动。

15. 发明申请

US20080082300A1 Design Structure for a Metal Fill Region of a Semiconductor Chip 审中-公开
标题翻译：半导体芯片的金属填充区域的设计结构
公开(公告)号：US20080082300A1
公开(公告)日：2008-04-03
申请号：US11868558
申请日：2007-10-08
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： G06F17/50
CPC分类号： H01L23/5222 , G06F17/5068 , G06F2217/12 , H01L2924/0002 , Y02P90/265 , H01L2924/00
摘要： A design structure embodied in a machine readable medium used in a design process includes a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括半导体芯片的金属填充区域，该半导体芯片包括半导体芯片的多个层组，每组包括第一金属填充层，第二金属填充层和包括设置在彼此平行的平面中的绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴垂直于所述金属的平面相交填充层和绝缘层，以及金属填充图案，其被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在所述第二金属填充层中的每个片的轴线线性移位在与每个金属填充轴正交的至少一个方向上。

16. 发明授权

US07142061B2 Balanced single ended to differential signal converter 有权
标题翻译：平衡单端到差分信号转换器
公开(公告)号：US07142061B2
公开(公告)日：2006-11-28
申请号：US11038706
申请日：2005-01-20
申请人： Salvatore N. Storino
发明人： Salvatore N. Storino
IPC分类号： H03F3/04
CPC分类号： G11C7/02 , G11C7/1078 , G11C7/1084
摘要： Techniques and circuits for generating a pair of differential signals with balanced switching between logical states from a single ended input signal are provided. The differential signals may be generated by controlling the switching of substantially identical driver stages with a set of control signals generated based on the single ended input signal.
摘要翻译：提供了用于从单端输入信号产生在逻辑状态之间平衡切换的一对差分信号的技术和电路。可以通过利用基于单端输入信号生成的一组控制信号来控制基本相同的驱动级的切换来产生差分信号。

17. 发明授权

US6084810A Dynamic logic circuit with bitline repeater circuit 失效
标题翻译：具有位线中继器电路的动态逻辑电路
公开(公告)号：US6084810A
公开(公告)日：2000-07-04
申请号：US233268
申请日：1999-01-19
申请人： Salvatore N. Storino , Gregory John Uhlmann
发明人： Salvatore N. Storino , Gregory John Uhlmann
IPC分类号： G11C7/12 , G11C7/00
CPC分类号： G11C7/12
摘要： A dynamic logic circuit is provided. The dynamic logic circuit includes at least one bitline. At least one repeater circuit is inserted into each bitline. The bitline repeater circuit includes an inverter and at least one transistor. The inverter is activated by the bitline starting to discharge and the activated inverter turns on the bitline repeater circuit transistor which discharges the bitline. The dynamic logic circuit including the bitline repeater circuit provides improved performance and decreased power consumption.
摘要翻译：提供动态逻辑电路。动态逻辑电路包括至少一个位线。每个位线插入至少一个中继器电路。位线中继器电路包括反相器和至少一个晶体管。变频器由位线开始放电激活，激活的反相器打开放电位线的位线中继器电路晶体管。包括位线中继器电路的动态逻辑电路提供了改善的性能并降低了功耗。

18. 发明授权

US08780604B2 State sensing system for eFuse memory 有权
标题翻译： eFuse存储器状态检测系统
公开(公告)号：US08780604B2
公开(公告)日：2014-07-15
申请号：US13535802
申请日：2012-06-28
申请人： Chihhung Liao , Phu Nguyen , Vimal R. Patel , George F. Paulik , Peder J. Paulson , Brian J. Reed , Salvatore N. Storino
发明人： Chihhung Liao , Phu Nguyen , Vimal R. Patel , George F. Paulik , Peder J. Paulson , Brian J. Reed , Salvatore N. Storino
IPC分类号： G11C17/12
CPC分类号： G06F17/5027 , G11C7/18 , G11C17/16 , G11C29/027 , G11C2029/4402
摘要： An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.
摘要翻译： eFuse电路可以包括字线，第一eFuse，第一逻辑门，第一blowFET和第一位线放电装置。第一eFuse可以具有耦合到字线的第一端和第二端。第一个eFuse可以在未吹塑时具有第一个阻力，当吹制时可能具有第二个阻力。第一逻辑门可以耦合到第一eFuse的第一端。第一逻辑门可能能够驱动足够的电流来吹动第一eFuse。第一blowFET可以具有耦合到第一电源电压的源极，耦合到编程信号的栅极和耦合到第一eFuse的第二端的漏极。第一位线放电装置可以具有耦合到第一eFuse的第二端的栅极，耦合到第一电源电压的源极和耦合到第一位线的漏极。

19. 发明授权

US07839715B2 SerDes double rate bitline with interlock to block precharge capture 失效
标题翻译： SerDes双倍位线与互锁以阻止预充电捕获
公开(公告)号：US07839715B2
公开(公告)日：2010-11-23
申请号：US12260376
申请日：2008-10-29
申请人： Leland Chang , Gary Ditlow , Robert K. Montoye , Salvatore N. Storino
发明人： Leland Chang , Gary Ditlow , Robert K. Montoye , Salvatore N. Storino
IPC分类号： G11C8/00
CPC分类号： H03M9/00 , H03K5/135
摘要： An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened.
摘要翻译：本发明的实施例提供了一种将早期时钟脉冲和后期时钟脉冲分离成两个不同锁存器的方法，其中通过位线产生早期时钟脉冲。响应于早期时钟脉冲上升，第一数据波形被发送到第四数据波形。响应于第三数据波形上升，早期预充电被关闭。响应于早期预充电的关闭并且响应于第五数据波形下降，如果第一数据波形具有值1，则第八数据波形上升。响应于第六数据波形上升，第一脉冲锁存器是开了

20. 发明授权

US07489039B2 Metal fill region of a semiconductor chip 失效
标题翻译：半导体芯片的金属填充区域
公开(公告)号：US07489039B2
公开(公告)日：2009-02-10
申请号：US11538118
申请日：2006-10-03
申请人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
发明人： Steven J. Baumgartner , Chun-Tao Li , Salvatore N. Storino , Mankit Wong
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.
摘要翻译：公开了一种半导体芯片的金属填充区域，其包括半导体芯片的多个层组，每组包括设置在彼此平行的平面中的第一金属填充层，第二金属填充层和绝缘层，设置在每个金属填充层中的多个金属填充片，每个片的金属填充片轴线，其中每个轴与任何参考点垂直地相交于所述金属填充层的平面和绝缘层，以及金属填充图案，被配置为定位所述片，使得所述第一金属填充层中的每个片的轴线在与所述金属填充轴中的每一个垂直的至少一个方向上在所述第二金属填充层中的每个片的轴线线性位移。

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