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11. 发明授权

US06977558B2 Self-adaptive voltage regulator for a phase-locked loop 失效
公开(公告)号：US06977558B2
公开(公告)日：2005-12-20
申请号：US10650396
申请日：2003-08-28
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus , Peter R. Seidel
IPC分类号： H03L7/08 , H03L7/14
CPC分类号： H03L7/08 , H03L2207/06
摘要： A self-adaptive voltage regulator for a phase-locked loop is disclosed. The phase-locked loop includes a phase detector, a charge pump, a low pass filter, and a voltage control oscillator, wherein the low pass filter inputs a control voltage to a voltage controlled oscillator for generation of an output clock. According to the method and system disclosed herein, the self-adaptive voltage regulator is coupled to an output of the low pass filter for sensing the control voltage during normal operation of the phase-locked loop, and for dynamically adjusting the supply voltage, which is input to the voltage controlled oscillator in response to the control voltage, such that the phase-locked loop maintains the control voltage within a predefined range of a reference voltage.

12. 发明授权

US4932023A Frame stripping protocol for early token release in a ring communication network 失效
标题翻译：在环通信网络中的早期令牌释放的帧去除协议
公开(公告)号：US4932023A
公开(公告)日：1990-06-05
申请号：US368739
申请日：1989-06-20
申请人： Joel Erwin Geyer , Joseph K. Lee , Vernon R. Norman , Kenneth T. Wilson
发明人： Joel Erwin Geyer , Joseph K. Lee , Vernon R. Norman , Kenneth T. Wilson
IPC分类号： H04L12/433
CPC分类号： H04L12/433
摘要： A frame stripping algorithm for use in a ring communication network utilizing early token release wherein multiple frames can exist on the ring at one time. The algorithm introduces two new strip terminating conditions which supplement two of the three conditions applicable to a normal token release scheme. The first of these conditions occurs when the source address in a received message is not the same as the receiving station's address and no code violation errors have been detected. The second condition occurs when the receiving station detects an isolated ending delimiter without a preceding starting delimiter.

13. 发明授权

US07512177B2 Method and apparatus for generating random jitter 失效
标题翻译：用于产生随机抖动的方法和装置
公开(公告)号：US07512177B2
公开(公告)日：2009-03-31
申请号：US11828390
申请日：2007-07-26
申请人： Hayden C. Cranford, Jr. , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Marcel A. Kossel , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译：装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为控制脉冲模式发生器。在一个方面，可调电容是至少一个变容二极管。另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到一对变容二极管。确定性抖动发生器可以耦合到脉冲图案发生器。可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。

14. 发明申请

US20080240224A1 STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY 审中-公开
标题翻译：一次性决策反馈均衡器（DFE）时钟和数据恢复的结构
公开(公告)号：US20080240224A1
公开(公告)日：2008-10-02
申请号：US12138214
申请日：2008-06-12
申请人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04L25/03057 , H04L2025/03356
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.
摘要翻译：一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的设计提供接收机并降低误码率（BER）。该设计通常包括接收器电路。接收器电路通常包括每位产生一个采样的判决反馈均衡器（DFE），以及用于自动自调整DFE的装置，以便当相位误差最小时能够在接收器电路内保持峰值能量的眼睛对中过程。

15. 发明申请

US20080133164A1 USING STATISTICAL SIGNATURES FOR TESTING HIGH-SPEED CIRCUITS 失效
标题翻译：使用统计信号测试高速电路
公开(公告)号：US20080133164A1
公开(公告)日：2008-06-05
申请号：US12021950
申请日：2008-01-29
申请人： Hayden C. Cranford , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford , Vernon R. Norman , Martin L. Schmatz
IPC分类号： G01R31/00 , G06F19/00
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译：公开了一种用于测试高速电路的方法和系统。该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。因此，可以确定高速电路是否在期望的参数内起作用。

16. 发明授权

US07317777B2 Digital adaptive control loop for data deserialization 失效
标题翻译：数字自适应控制回路用于数据反序列化
公开(公告)号：US07317777B2
公开(公告)日：2008-01-08
申请号：US10265759
申请日：2002-10-07
申请人： Hayden C Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L25/00
CPC分类号： H03L7/091 , H04L7/0337
摘要： A system and method for tracking/adapting phase or frequency changes in an incoming serial data stream that may contain significant amounts of noise and/or jitter and may contain relatively long periods of successive univalue data bits. The method includes digitally sampling a received data stream at predefined intervals to produce a data set; estimating when logic transitions occur in the data set; detecting a timing trend represented by the estimated logic transitions; and adjusting a frequency of the first clock so that the timing trend averages approximately zero over a plurality of logic transitions.
摘要翻译：用于跟踪/调整可能包含大量噪声和/或抖动的输入串行数据流中的相位或频率变化的系统和方法，并且可以包含相对较长的连续的单值数据位。该方法包括以预定的间隔对接收的数据流进行数字采样以产生数据集; 在数据集中发生逻辑转换时估计; 检测由所估计的逻辑转换表示的定时趋势; 以及调整所述第一时钟的频率，使得所述时序趋势在多个逻辑转换中平均为零。

17. 发明授权

US07279950B2 Method and system for high frequency clock signal gating 失效
公开(公告)号：US07279950B2
公开(公告)日：2007-10-09
申请号：US11235758
申请日：2005-09-27
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Samuel T. Ray , Wayne A. Utter
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Samuel T. Ray , Wayne A. Utter
IPC分类号： H03K3/00
CPC分类号： G06F1/04
摘要： A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal responsive to a first clock signal pulse negative half. The buffer provides second and successive clock signal pulses occurring immediately and sequentially after the first clock signal pulse as a buffer clock signal output to a second buffer stage in a second stage clock path, each having the nominal clock amplitude and the nominal clock pulse width of the clock signal without jitter.

18. 发明授权

US07042277B2 Circuit and method for reducing jitter in a PLL of high speed serial links 失效
标题翻译：用于降低高速串行链路PLL的抖动的电路和方法
公开(公告)号：US07042277B2
公开(公告)日：2006-05-09
申请号：US10685022
申请日：2003-10-14
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Vernon R. Norman , Todd M. Rasmus
IPC分类号： G01F1/10
CPC分类号： H03L7/10
摘要： Aspects for reducing jitter in a PLL of a high speed serial link include examining at least one parameter related to performance of a voltage controlled oscillator (VCO) in the PLL, and controlling adjustment of a supply voltage to the VCO based on the examining. A regulator control circuit performs the examining and controlling.
摘要翻译：降低高速串行链路的PLL中的抖动的方面包括检查与PLL中的压控振荡器（VCO）的性能有关的至少一个参数，以及基于检查来控制对VCO的电源电压的调整。调节器控制电路进行检查和控制。

19. 发明授权

US07809054B2 One-sample-per-bit decision feedback equalizer (DFE) clock and data recovery 失效
标题翻译：单采样每位决策反馈均衡器（DFE）时钟和数据恢复
公开(公告)号：US07809054B2
公开(公告)日：2010-10-05
申请号：US11405997
申请日：2006-04-18
申请人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： Juan A. Carballo , Hayden C. Cranford, Jr. , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L25/03063
摘要： Disclosed are a receiver circuit, method and design architecture of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER). An integrating receiver is combined with a decision feedback equalizer along with the appropriate (CDR) loop phase detector to maintain a single sample per bit requirement. The incoming voltage is converted to a current and connected to a current summing node. Weighted currents determined by the values of previously detected bits and their respective feedback coefficients are also connected to this node. Additionally, the summed currents is integrated and converted to a voltage. A sampler is utilized to make a bit decision based on the resulting voltage. After sampling, the integrator is reset before analysis of the next bit. The necessary amplification is achieved by maximizing the sensitivity of the latch, using integration in front of the data latch.
摘要翻译：公开了一种在接收机中利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的接收器电路，方法和设计架构，并且降低了误码率（BER ）。集成接收机与决策反馈均衡器以及适当的（CDR）环路相位检测器相结合，以保持每位需求的单个采样。输入电压被转换为电流并连接到电流求和节点。由先前检测到的位及其各自的反馈系数的值确定的加权电流也连接到该节点。另外，总和电流被积分并转换成电压。采样器用于基于所得到的电压进行位决定。采样后，积分器在分析下一位之前被复位。通过使用在数据锁存器前面的积分来最大化锁存器的灵敏度来实现必要的放大。

20. 发明授权

US07661052B2 Using statistical signatures for testing high-speed circuits 失效
标题翻译：使用统计特征来测试高速电路
公开(公告)号：US07661052B2
公开(公告)日：2010-02-09
申请号：US12021950
申请日：2008-01-29
申请人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
发明人： Hayden C. Cranford, Jr. , Vernon R. Norman , Martin L. Schmatz
IPC分类号： G06F11/277 , G06F11/16
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译：公开了一种用于测试高速电路的方法和系统。该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。因此，可以确定高速电路是否在期望的参数内起作用。

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