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11. 发明授权

US06647004B2 Network switch using network processor and methods 失效
公开(公告)号：US06647004B2
公开(公告)日：2003-11-11
申请号：US10003981
申请日：2001-10-23
申请人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： James Johnson Allen, Jr. , Brian Mitchell Bass , Jean Louis Calvignac , Santosh Prasad Gaur , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04B7216
CPC分类号： H04Q3/002 , H04L45/742 , H04L49/254 , H04L49/351 , H04L49/354 , H04L49/602 , H04L2212/00 , H04Q3/5455 , H04Q2213/1302 , H04Q2213/13034 , H04Q2213/1304 , H04Q2213/13103 , H04Q2213/13104 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13322
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation among a plurality of interface processors and a suite of peripheral elements formed on a semiconductor substrate. The interface processors and peripherals together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.

12. 发明授权

US06460120B1 Network processor, memory organization and methods 失效
标题翻译：网络处理器，内存组织和方法
公开(公告)号：US06460120B1
公开(公告)日：2002-10-01
申请号：US09384744
申请日：1999-08-27
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Piyush Chunilal Patel , Juan Guillermo Revilla , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Piyush Chunilal Patel , Juan Guillermo Revilla , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F1300
CPC分类号： H04Q11/0478 , H04L2012/5681
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a plurality of memory elements and a plurality of interface processors formed on a semiconductor substrate. The memory elements and interface processors together form a network processor capable of cooperating with other elements in executing instructions directing the flow of data in a network. Access to the memory elements is controlled in a particular manner and under operative rules which provide controlled multiple accesses of the plurality of memory elements by the plurality of processors.
摘要翻译：一种网络交换设备，用于这种设备的部件，以及操作这样的设备的方法，其中通过多个存储器元件和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。存储器元件和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令中与其它元件协作。存储元件的访问以特定方式和操作规则进行控制，这些规则由多个处理器提供对多个存储器元件的受控多次访问。

13. 发明授权

US06449576B1 Network processor probing and port mirroring 失效
标题翻译：网络处理器探测和端口镜像
公开(公告)号：US06449576B1
公开(公告)日：2002-09-10
申请号：US09538247
申请日：2000-03-29
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken , Chad Everett Winemiller
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken , Chad Everett Winemiller
IPC分类号： G01R2728
CPC分类号： H04L43/50 , G01R31/31926
摘要： A method and system for systematically accessing and monitoring operating parameter signals within an IC device. A probe configuration logic selects a subset of signals from among a set of available signals within a physical or logical subdivision of the IC device. Signal access logic selectively provides physical or logical access from the selected subset of signals within the physical or logical subdivision of the IC device to a probe sensor, such that IC device operations may be flexibly and comprehensively monitored. A local mode selector provides remote access to the selected subset of signals at an input/output (I/O) data interface. Data packaging logic in communication with the probe sensor permits port mirroring of the I/O data interface.
摘要翻译：一种用于系统地访问和监视IC设备内的操作参数信号的方法和系统。探针配置逻辑从IC器件的物理或逻辑细分内的一组可用信号中选择一个信号子集。信号访问逻辑选择性地从IC器件的物理或逻辑细分中的选定的信号子集提供到探针传感器的物理或逻辑访问，使得可以灵活和全面地监视IC器件操作。本地模式选择器可在输入/输出（I / O）数据接口上远程访问选定的信号子集。与探头传感器通信的数据封装逻辑允许端口镜像I / O数据接口。

14. 发明授权

US07984038B2 Longest prefix match (LPM) algorithm implementation for a network processor 失效
标题翻译：用于网络处理器的最长前缀匹配（LPM）算法实现
公开(公告)号：US07984038B2
公开(公告)日：2011-07-19
申请号：US12103140
申请日：2008-04-15
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , H04L45/7457 , Y10S707/99931 , Y10S707/99933 , Y10S707/99936 , Y10S707/99942 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.
摘要翻译：当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。要找到完全匹配或最匹配的前缀，模式必须一次比较一下，直到发现确切或第一个匹配。这需要“n”个比较或存储器访问来识别最接近的匹配模式。树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

15. 发明授权

US07953951B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07953951B2
公开(公告)日：2011-05-31
申请号：US12124396
申请日：2008-05-21
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

16. 发明授权

US07903687B2 Method for scheduling, writing, and reading data inside the partitioned buffer of a switch, router or packet processing device 失效
标题翻译：在交换机，路由器或分组处理设备的分区缓冲区内调度，写入和读取数据的方法
公开(公告)号：US07903687B2
公开(公告)日：2011-03-08
申请号：US11096363
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04J3/16 , H04J3/22 , H04J3/24
CPC分类号： H04L49/901 , H04J3/0632 , H04L47/50 , H04L49/90 , H04L49/9031
摘要： A method for receiving packets in a computer network are disclosed. The method include providing at least one receive port, a buffer, a scheduler, and a wrap port. The buffer has an input coupled with the at least one receive port and an output. The scheduler has a first input coupled to the output of the buffer, a second input coupled to the wrap port, and an output.
摘要翻译：公开了一种在计算机网络中接收分组的方法。该方法包括提供至少一个接收端口，缓冲器，调度器和包装端口。缓冲器具有与至少一个接收端口和输出端耦合的输入。调度器具有耦合到缓冲器的输出的第一输入，耦合到包装端口的第二输入和输出。

17. 发明授权

US07782888B2 Configurable ports for a host ethernet adapter 有权
标题翻译：主机以太网适配器的可配置端口
公开(公告)号：US07782888B2
公开(公告)日：2010-08-24
申请号：US11953820
申请日：2007-12-10
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin B. Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L12/40032 , H04L12/413 , H04L49/90 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/18 , H04L69/323 , H04L69/324
摘要： A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.
摘要翻译：根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。最后，该系统允许适配器为多个数据源使用相同的引脚。

18. 发明授权

US07697536B2 Network communications for operating system partitions 有权
标题翻译：操作系统分区的网络通信
公开(公告)号：US07697536B2
公开(公告)日：2010-04-13
申请号：US11097051
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg , Kyle A. Lucke , Harvey G. Kiel
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg , Kyle A. Lucke , Harvey G. Kiel
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , H04L49/90 , H04L69/32
摘要： Providing communications between operating system partitions and a computer network. In one aspect, an apparatus for distributing network communications among multiple operating system partitions includes a physical port allowing communications between the network and the computer system, and logical ports associated with the physical port, where each logical port is associated with one of the operating system partitions. Each of the logical ports enables communication between a physical port and the associated operating system partition and allows configurability of network resources of the system. Other aspects include a logical switch for logical and physical ports, and packet queues for each connection and for each logical port.
摘要翻译：提供操作系统分区与计算机网络之间的通信。一方面，一种用于在多个操作系统分区之间分配网络通信的装置包括允许网络和计算机系统之间的通信的物理端口以及与物理端口相关联的逻辑端口，其中每个逻辑端口与操作系统之一相关联分区。每个逻辑端口实现物理端口与相关联的操作系统分区之间的通信，并允许系统的网络资源的可配置性。其他方面包括用于逻辑和物理端口的逻辑交换机，以及每个连接和每个逻辑端口的分组队列。

19. 发明授权

US07603539B2 Systems and methods for multi-frame control blocks 有权
标题翻译：多帧控制块的系统和方法
公开(公告)号：US07603539B2
公开(公告)日：2009-10-13
申请号：US12039304
申请日：2008-02-28
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

20. 发明授权

US07469332B2 Systems and methods for adaptively mapping an instruction cache 失效
标题翻译：用于自适应地映射指令高速缓存的系统和方法
公开(公告)号：US07469332B2
公开(公告)日：2008-12-23
申请号：US11070758
申请日：2005-03-02
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Harm Peter Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Harm Peter Hofstee , Jens Leenstra , Hans-Werner Tast , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F9/355
CPC分类号： G06F12/0864
摘要： Systems and methods for adaptively mapping system memory address bits into an instruction tag and an index into the cache are disclosed. More particularly, hardware and software are disclosed for observing collisions that occur for a given mapping of system memory bits into a tag and an index. Based on the observations, an optimal mapping may be determined that minimizes collisions.
摘要翻译：公开了用于将系统存储器地址位自适应地映射到指令标签和到高速缓存中的索引的系统和方法。更具体地，公开了用于观察对于系统存储器位给定到标签和索引的映射而出现的冲突的硬件和软件。基于观察结果，可以确定最小化碰撞的最佳映射。

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